AS - Online Linux Manual PageSection : 1
Updated : 2023-01-18
Source : binutils-2.39
Note : GNU Development Tools
NAMEAS − the portable GNU assembler.
SYNOPSISas [−a[cdghlns][=file]] [−−alternate] [−D]
[−−compress−debug−sections] [−−nocompress−debug−sections]
[−−debug−prefix−map old=new]
[−−defsym sym=val] [−f] [−g] [−−gstabs]
[−−gstabs+] [−−gdwarf−<N>] [−−gdwarf−sections]
[−−gdwarf−cie−version=VERSION]
[−−help] [−I dir] [−J]
[−K] [−L] [−−listing−lhs−width=NUM]
[−−listing−lhs−width2=NUM] [−−listing−rhs−width=NUM]
[−−listing−cont−lines=NUM] [−−keep−locals]
[−−no−pad−sections]
[−o objfile] [−R]
[−−statistics]
[−v] [−version] [−−version]
[−W] [−−warn] [−−fatal−warnings] [−w] [−x]
[−Z] [@FILE]
[−−sectname−subst] [−−size−check=[error|warning]]
[−−elf−stt−common=[no|yes]]
[−−generate−missing−build−notes=[no|yes]]
[−−multibyte−handling=[allow|warn|warn−sym−only]]
[−−target−help] [target-options]
[−−|files ...]
TARGETTarget AArch64 options:
[−EB|−EL]
[−mabi=ABI] Target Alpha options:
[−mcpu]
[−mdebug | −no−mdebug]
[−replace | −noreplace]
[−relax] [−g] [−Gsize]
[−F] [−32addr] Target ARC options:
[−mcpu=cpu]
[−mA6|−mARC600|−mARC601|−mA7|−mARC700|−mEM|−mHS]
[−mcode−density]
[−mrelax]
[−EB|−EL] Target ARM options:
[−mcpu=processor[+extension...]]
[−march=architecture[+extension...]]
[−mfpu=floating-point-format]
[−mfloat−abi=abi]
[−meabi=ver]
[−mthumb]
[−EB|−EL]
[−mapcs−32|−mapcs−26|−mapcs−float|
−mapcs−reentrant]
[−mthumb−interwork] [−k] Target Blackfin options:
[−mcpu=processor[−sirevision]]
[−mfdpic]
[−mno−fdpic]
[−mnopic] Target BPF options:
[−EL] [−EB] Target CRIS options:
[−−underscore | −−no−underscore]
[−−pic] [−N]
[−−emulation=criself | −−emulation=crisaout]
[−−march=v0_v10 | −−march=v10 | −−march=v32 | −−march=common_v10_v32] Target C−SKY options:
[−march=arch] [−mcpu=cpu]
[−EL] [−mlittle−endian] [−EB] [−mbig−endian]
[−fpic] [−pic]
[−mljump] [−mno−ljump]
[−force2bsr] [−mforce2bsr] [−no−force2bsr] [−mno−force2bsr]
[−jsri2bsr] [−mjsri2bsr] [−no−jsri2bsr ] [−mno−jsri2bsr]
[−mnolrw ] [−mno−lrw]
[−melrw] [−mno−elrw]
[−mlaf ] [−mliterals−after−func]
[−mno−laf] [−mno−literals−after−func]
[−mlabr] [−mliterals−after−br]
[−mno−labr] [−mnoliterals−after−br]
[−mistack] [−mno−istack]
[−mhard−float] [−mmp] [−mcp] [−mcache]
[−msecurity] [−mtrust]
[−mdsp] [−medsp] [−mvdsp] Target D10V options:
[−O] Target D30V options:
[−O|−n|−N] Target EPIPHANY options:
[−mepiphany|−mepiphany16] Target H8/300 options:
[−h−tick−hex] Target i386 options:
[−−32|−−x32|−−64] [−n]
[−march=CPU[+EXTENSION...]] [−mtune=CPU] Target IA−64 options:
[−mconstant−gp|−mauto−pic]
[−milp32|−milp64|−mlp64|−mp64]
[−mle|mbe]
[−mtune=itanium1|−mtune=itanium2]
[−munwind−check=warning|−munwind−check=error]
[−mhint.b=ok|−mhint.b=warning|−mhint.b=error]
[−x|−xexplicit] [−xauto] [−xdebug] Target IP2K options:
[−mip2022|−mip2022ext] Target M32C options:
[−m32c|−m16c] [−relax] [−h−tick−hex] Target M32R options:
[−−m32rx|−−[no−]warn−explicit−parallel−conflicts|
−−W[n]p] Target M680X0 options:
[−l] [−m68000|−m68010|−m68020|...] Target M68HC11 options:
[−m68hc11|−m68hc12|−m68hcs12|−mm9s12x|−mm9s12xg]
[−mshort|−mlong]
[−mshort−double|−mlong−double]
[−−force−long−branches] [−−short−branches]
[−−strict−direct−mode] [−−print−insn−syntax]
[−−print−opcodes] [−−generate−example] Target MCORE options:
[−jsri2bsr] [−sifilter] [−relax]
[−mcpu=[210|340]] Target Meta options:
[−mcpu=cpu] [−mfpu=cpu] [−mdsp=cpu] Target MICROBLAZE options: Target MIPS options:
[−nocpp] [−EL] [−EB] [−O[optimization level]]
[−g[debug level]] [−G num] [−KPIC] [−call_shared]
[−non_shared] [−xgot [−mvxworks−pic]
[−mabi=ABI] [−32] [−n32] [−64] [−mfp32] [−mgp32]
[−mfp64] [−mgp64] [−mfpxx]
[−modd−spreg] [−mno−odd−spreg]
[−march=CPU] [−mtune=CPU] [−mips1] [−mips2]
[−mips3] [−mips4] [−mips5] [−mips32] [−mips32r2]
[−mips32r3] [−mips32r5] [−mips32r6] [−mips64] [−mips64r2]
[−mips64r3] [−mips64r5] [−mips64r6]
[−construct−floats] [−no−construct−floats]
[−mignore−branch−isa] [−mno−ignore−branch−isa]
[−mnan=encoding]
[−trap] [−no−break] [−break] [−no−trap]
[−mips16] [−no−mips16]
[−mmips16e2] [−mno−mips16e2]
[−mmicromips] [−mno−micromips]
[−msmartmips] [−mno−smartmips]
[−mips3d] [−no−mips3d]
[−mdmx] [−no−mdmx]
[−mdsp] [−mno−dsp]
[−mdspr2] [−mno−dspr2]
[−mdspr3] [−mno−dspr3]
[−mmsa] [−mno−msa]
[−mxpa] [−mno−xpa]
[−mmt] [−mno−mt]
[−mmcu] [−mno−mcu]
[−mcrc] [−mno−crc]
[−mginv] [−mno−ginv]
[−mloongson−mmi] [−mno−loongson−mmi]
[−mloongson−cam] [−mno−loongson−cam]
[−mloongson−ext] [−mno−loongson−ext]
[−mloongson−ext2] [−mno−loongson−ext2]
[−minsn32] [−mno−insn32]
[−mfix7000] [−mno−fix7000]
[−mfix−rm7000] [−mno−fix−rm7000]
[−mfix−vr4120] [−mno−fix−vr4120]
[−mfix−vr4130] [−mno−fix−vr4130]
[−mfix−r5900] [−mno−fix−r5900]
[−mdebug] [−no−mdebug]
[−mpdr] [−mno−pdr] Target MMIX options:
[−−fixed−special−register−names] [−−globalize−symbols]
[−−gnu−syntax] [−−relax] [−−no−predefined−symbols]
[−−no−expand] [−−no−merge−gregs] [−x]
[−−linker−allocated−gregs] Target Nios II options:
[−relax−all] [−relax−section] [−no−relax]
[−EB] [−EL] Target NDS32 options:
[−EL] [−EB] [−O] [−Os] [−mcpu=cpu]
[−misa=isa] [−mabi=abi] [−mall−ext]
[−m[no−]16−bit] [−m[no−]perf−ext] [−m[no−]perf2−ext]
[−m[no−]string−ext] [−m[no−]dsp−ext] [−m[no−]mac] [−m[no−]div]
[−m[no−]audio−isa−ext] [−m[no−]fpu−sp−ext] [−m[no−]fpu−dp−ext]
[−m[no−]fpu−fma] [−mfpu−freg=FREG] [−mreduced−regs]
[−mfull−regs] [−m[no−]dx−regs] [−mpic] [−mno−relax]
[−mb2bb] Target PDP11 options:
[−mpic|−mno−pic] [−mall] [−mno−extensions]
[−mextension|−mno−extension]
[−mcpu] [−mmachine] Target picoJava options:
[−mb|−me] Target PowerPC options:
[−a32|−a64]
[−mpwrx|−mpwr2|−mpwr|−m601|−mppc|−mppc32|−m603|−m604|−m403|−m405|
−m440|−m464|−m476|−m7400|−m7410|−m7450|−m7455|−m750cl|−mgekko|
−mbroadway|−mppc64|−m620|−me500|−e500x2|−me500mc|−me500mc64|−me5500|
−me6500|−mppc64bridge|−mbooke|−mpower4|−mpwr4|−mpower5|−mpwr5|−mpwr5x|
−mpower6|−mpwr6|−mpower7|−mpwr7|−mpower8|−mpwr8|−mpower9|−mpwr9−ma2|
−mcell|−mspe|−mspe2|−mtitan|−me300|−mcom]
[−many] [−maltivec|−mvsx|−mhtm|−mvle]
[−mregnames|−mno−regnames]
[−mrelocatable|−mrelocatable−lib|−K PIC] [−memb]
[−mlittle|−mlittle−endian|−le|−mbig|−mbig−endian|−be]
[−msolaris|−mno−solaris]
[−nops=count] Target PRU options:
[−link−relax]
[−mnolink−relax]
[−mno−warn−regname−label] Target RISC-V options:
[−fpic|−fPIC|−fno−pic]
[−march=ISA]
[−mabi=ABI]
[−mlittle−endian|−mbig−endian] Target RL78 options:
[−mg10]
[−m32bit−doubles|−m64bit−doubles] Target RX options:
[−mlittle−endian|−mbig−endian]
[−m32bit−doubles|−m64bit−doubles]
[−muse−conventional−section−names]
[−msmall−data−limit]
[−mpid]
[−mrelax]
[−mint−register=number]
[−mgcc−abi|−mrx−abi] Target s390 options:
[−m31|−m64] [−mesa|−mzarch] [−march=CPU]
[−mregnames|−mno−regnames]
[−mwarn−areg−zero] Target SCORE options:
[−EB][−EL][−FIXDD][−NWARN]
[−SCORE5][−SCORE5U][−SCORE7][−SCORE3]
[−march=score7][−march=score3]
[−USE_R1][−KPIC][−O0][−G num][−V] Target SPARC options:
[−Av6|−Av7|−Av8|−Aleon|−Asparclet|−Asparclite
−Av8plus|−Av8plusa|−Av8plusb|−Av8plusc|−Av8plusd
−Av8plusv|−Av8plusm|−Av9|−Av9a|−Av9b|−Av9c
−Av9d|−Av9e|−Av9v|−Av9m|−Asparc|−Asparcvis
−Asparcvis2|−Asparcfmaf|−Asparcima|−Asparcvis3
−Asparcvisr|−Asparc5]
[−xarch=v8plus|−xarch=v8plusa]|−xarch=v8plusb|−xarch=v8plusc
−xarch=v8plusd|−xarch=v8plusv|−xarch=v8plusm|−xarch=v9
−xarch=v9a|−xarch=v9b|−xarch=v9c|−xarch=v9d|−xarch=v9e
−xarch=v9v|−xarch=v9m|−xarch=sparc|−xarch=sparcvis
−xarch=sparcvis2|−xarch=sparcfmaf|−xarch=sparcima
−xarch=sparcvis3|−xarch=sparcvisr|−xarch=sparc5
−bump]
[−32|−64]
[−−enforce−aligned−data][−−dcti−couples−detect] Target TIC54X options:
[−mcpu=54[123589]|−mcpu=54[56]lp] [−mfar−mode|−mf]
[−merrors−to−file <filename>|−me <filename>] Target TIC6X options:
[−march=arch] [−mbig−endian|−mlittle−endian]
[−mdsbt|−mno−dsbt] [−mpid=no|−mpid=near|−mpid=far]
[−mpic|−mno−pic] Target TILE-Gx options:
[−m32|−m64][−EB][−EL] Target Visium options:
[−mtune=arch] Target Xtensa options:
[−−[no−]text−section−literals] [−−[no−]auto−litpools]
[−−[no−]absolute−literals]
[−−[no−]target−align] [−−[no−]longcalls]
[−−[no−]transform]
[−−rename−section oldname=newname]
[−−[no−]trampolines]
[−−abi−windowed|−−abi−call0] Target Z80 options:
[−march=CPU[−EXT][+EXT]]
[−local−prefix=PREFIX]
[−colonless]
[−sdcc]
[−fp−s=FORMAT]
[−fp−d=FORMAT]
DESCRIPTIONGNU as is really a family of assemblers. If you use (or have used) the GNU assembler on one architecture, you should find a fairly similar environment when you use it on another architecture. Each version has much in common with the others, including object file formats, most assembler directives (often called pseudo-ops) and assembler syntax. as is primarily intended to assemble the output of the GNU C compiler \*(C`gcc\*(C'\fR for use by the linker \*(C`ld\*(C'\fR. Nevertheless, we've tried to make \fBas\fR assemble correctly everything that other assemblers for the same machine would assemble. Any exceptions are documented explicitly. This doesn't mean as always uses the same syntax as another assembler for the same architecture; for example, we know of several incompatible versions of 680x0 assembly language syntax. Each time you run as it assembles exactly one source program. The source program is made up of one or more files. (The standard input is also a file.) You give as a command line that has zero or more input file names. The input files are read (from left file name to right). A command-line argument (in any position) that has no special meaning is taken to be an input file name. If you give as no file names it attempts to read one input file from the as standard input, which is normally your terminal. You may have to type ctl-D to tell as there is no more program to assemble. Use −− if you need to explicitly name the standard input file in your command line. If the source is empty, as produces a small, empty object file. as may write warnings and error messages to the standard error file (usually your terminal). This should not happen when a compiler runs as automatically. Warnings report an assumption made so that as could keep assembling a flawed program; errors report a grave problem that stops the assembly. If you are invoking as via the GNU C compiler, you can use the −Wa option to pass arguments through to the assembler. The assembler arguments must be separated from each other (and the −Wa) by commas. For example: gcc −c −g −O −Wa,−alh,−L file.c
This passes two options to the assembler: −alh (emit a listing to standard output with high-level and assembly source) and −L (retain local symbols in the symbol table). Usually you do not need to use this −Wa mechanism, since many compiler command-line options are automatically passed to the assembler by the compiler. (You can call the GNU compiler driver with the −v option to see precisely what options it passes to each compilation pass, including the assembler.)
OPTIONS@file Read command-line options from file. The options read are inserted in place of the original @file option. If file does not exist, or cannot be read, then the option will be treated literally, and not removed. Options in file are separated by whitespace. A whitespace character may be included in an option by surrounding the entire option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The file may itself contain additional @file options; any such options will be processed recursively. −a[cdghlmns] Turn on listings, in any of a variety of ways: −ac omit false conditionals −ad omit debugging directives −ag include general information, like as version and options passed −ah include high-level source −al include assembly −am include macro expansions −an omit forms processing −as include symbols =file set the name of the listing file You may combine these options; for example, use −aln for assembly listing without forms processing. The =file option, if used, must be the last one. By itself, −a defaults to −ahls. −−alternate Begin in alternate macro mode. −−compress−debug−sections Compress DWARF debug sections using zlib with SHF_COMPRESSED from the ELF ABI. The resulting object file may not be compatible with older linkers and object file utilities. Note if compression would make a given section larger then it is not compressed. −−compress−debug−sections=none −−compress−debug−sections=zlib −−compress−debug−sections=zlib−gnu −−compress−debug−sections=zlib−gabi These options control how DWARF debug sections are compressed. −−compress−debug−sections=none is equivalent to −−nocompress−debug−sections. −−compress−debug−sections=zlib and −−compress−debug−sections=zlib−gabi are equivalent to −−compress−debug−sections. −−compress−debug−sections=zlib−gnu compresses DWARF debug sections using zlib. The debug sections are renamed to begin with .zdebug. Note if compression would make a given section larger then it is not compressed nor renamed. −−nocompress−debug−sections Do not compress DWARF debug sections. This is usually the default for all targets except the x86/x86_64, but a configure time option can be used to override this. −D Ignored. This option is accepted for script compatibility with calls to other assemblers. −−debug−prefix−map old=new When assembling files in directory old, record debugging information describing them as in new instead. −−defsym sym=value Define the symbol sym to be value before assembling the input file. value must be an integer constant. As in C, a leading 0x indicates a hexadecimal value, and a leading 0 indicates an octal value. The value of the symbol can be overridden inside a source file via the use of a \*(C`.set\*(C'\fR pseudo-op. −f "fast"−−−skip whitespace and comment preprocessing (assume source is compiler output). −g −−gen−debug Generate debugging information for each assembler source line using whichever debug format is preferred by the target. This currently means either STABS, ECOFF or DWARF2. When the debug format is DWARF then a \*(C`.debug_info\*(C'\fR and \*(C`.debug_line\*(C'\fR section is only emitted when the assembly file doesn't generate one itself. −−gstabs Generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. −−gstabs+ Generate stabs debugging information for each assembler line, with GNU extensions that probably only gdb can handle, and that could make other debuggers crash or refuse to read your program. This may help debugging assembler code. Currently the only GNU extension is the location of the current working directory at assembling time. −−gdwarf−2 Generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note−−−this option is only supported by some targets, not all of them. −−gdwarf−3 This option is the same as the −−gdwarf−2 option, except that it allows for the possibility of the generation of extra debug information as per version 3 of the DWARF specification. Note − enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis. −−gdwarf−4 This option is the same as the −−gdwarf−2 option, except that it allows for the possibility of the generation of extra debug information as per version 4 of the DWARF specification. Note − enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis. −−gdwarf−5 This option is the same as the −−gdwarf−2 option, except that it allows for the possibility of the generation of extra debug information as per version 5 of the DWARF specification. Note − enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis. −−gdwarf−sections Instead of creating a .debug_line section, create a series of .debug_line.foo sections where foo is the name of the corresponding code section. For example a code section called .text.func will have its dwarf line number information placed into a section called .debug_line.text.func. If the code section is just called .text then debug line section will still be called just .debug_line without any suffix. −−gdwarf−cie−version=version Control which version of DWARF Common Information Entries (CIEs) are produced. When this flag is not specificed the default is version 1, though some targets can modify this default. Other possible values for version are 3 or 4. −−size−check=error −−size−check=warning Issue an error or warning for invalid ELF .size directive. −−elf−stt−common=no −−elf−stt−common=yes These options control whether the ELF assembler should generate common symbols with the \*(C`STT_COMMON\*(C'\fR type. The default can be controlled by a configure option −−enable−elf−stt−common. −−generate−missing−build−notes=yes −−generate−missing−build−notes=no These options control whether the ELF assembler should generate GNU Build attribute notes if none are present in the input sources. The default can be controlled by the −−enable−generate−build−notes configure option. −−help Print a summary of the command-line options and exit. −−target−help Print a summary of all target specific options and exit. −I dir Add directory dir to the search list for \*(C`.include\*(C'\fR directives. −J Don't warn about signed overflow. −K Issue warnings when difference tables altered for long displacements. −L −−keep−locals Keep (in the symbol table) local symbols. These symbols start with system-specific local label prefixes, typically .L for ELF systems or L for traditional a.out systems. −−listing−lhs−width=number Set the maximum width, in words, of the output data column for an assembler listing to number. −−listing−lhs−width2=number Set the maximum width, in words, of the output data column for continuation lines in an assembler listing to number. −−listing−rhs−width=number Set the maximum width of an input source line, as displayed in a listing, to number bytes. −−listing−cont−lines=number Set the maximum number of lines printed in a listing for a single line of input to number + 1. −−multibyte−handling=allow −−multibyte−handling=warn −−multibyte−handling=warn−sym−only Controls how the assembler handles multibyte characters in the input. The default (which can be restored by using the allow argument) is to allow such characters without complaint. Using the warn argument will make the assembler generate a warning message whenever any multibyte character is encountered. Using the warn-sym-only argument will only cause a warning to be generated when a symbol is defined with a name that contains multibyte characters. (References to undefined symbols will not generate a warning). −−no−pad−sections Stop the assembler for padding the ends of output sections to the alignment of that section. The default is to pad the sections, but this can waste space which might be needed on targets which have tight memory constraints. −o objfile Name the object-file output from as objfile. −R Fold the data section into the text section. −−sectname−subst Honor substitution sequences in section names. −−statistics Print the maximum space (in bytes) and total time (in seconds) used by assembly. −−strip−local−absolute Remove local absolute symbols from the outgoing symbol table. −v −version Print the as version. −−version Print the as version and exit. −W −−no−warn Suppress warning messages. −−fatal−warnings Treat warnings as errors. −−warn Don't suppress warning messages or treat them as errors. −w Ignored. −x Ignored. −Z Generate an object file even after errors. −− | files ... Standard input, or source files to assemble. The following options are available when as is configured for the 64−bit mode of the ARM Architecture (AArch64). −EB This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor. −EL This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor. −mabi=abi Specify which ABI the source code uses. The recognized arguments are: \*(C`ilp32\*(C'\fR and \f(CW\*(C`lp64\*(C'\fR, which decides the generated object file in ELF32 and ELF64 format respectively. The default is \*(C`lp64\*(C'\fR. −mcpu=processor[+extension...] This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: \*(C`cortex\-a34\*(C'\fR, \*(C`cortex\-a35\*(C'\fR, \*(C`cortex\-a53\*(C'\fR, \*(C`cortex\-a55\*(C'\fR, \*(C`cortex\-a57\*(C'\fR, \*(C`cortex\-a65\*(C'\fR, \*(C`cortex\-a65ae\*(C'\fR, \*(C`cortex\-a72\*(C'\fR, \*(C`cortex\-a73\*(C'\fR, \*(C`cortex\-a75\*(C'\fR, \*(C`cortex\-a76\*(C'\fR, \*(C`cortex\-a76ae\*(C'\fR, \*(C`cortex\-a77\*(C'\fR, \*(C`cortex\-a78\*(C'\fR, \*(C`cortex\-a78ae\*(C'\fR, \*(C`cortex\-a78c\*(C'\fR, \*(C`cortex\-a510\*(C'\fR, \*(C`cortex\-a710\*(C'\fR, \*(C`ares\*(C'\fR, \*(C`exynos\-m1\*(C'\fR, \*(C`falkor\*(C'\fR, \*(C`neoverse\-n1\*(C'\fR, \*(C`neoverse\-n2\*(C'\fR, \*(C`neoverse\-e1\*(C'\fR, \*(C`neoverse\-v1\*(C'\fR, \*(C`qdf24xx\*(C'\fR, \*(C`saphira\*(C'\fR, \*(C`thunderx\*(C'\fR, \*(C`vulcan\*(C'\fR, \*(C`xgene1\*(C'\fR \*(C`xgene2\*(C'\fR, \*(C`cortex\-r82\*(C'\fR, \*(C`cortex\-x1\*(C'\fR, and \*(C`cortex\-x2\*(C'\fR. The special name \*(C`all\*(C'\fR may be used to allow the assembler to accept instructions valid for any supported processor, including all optional extensions. In addition to the basic instruction set, the assembler can be told to accept, or restrict, various extension mnemonics that extend the processor. If some implementations of a particular processor can have an extension, then then those extensions are automatically enabled. Consequently, you will not normally have to specify any additional extensions. −march=architecture[+extension...] This option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. The following architecture names are recognized: \*(C`armv8\-a\*(C'\fR, \*(C`armv8.1\-a\*(C'\fR, \f(CW\*(C`armv8.2\-a\*(C'\fR, \f(CW\*(C`armv8.3\-a\*(C'\fR, \f(CW\*(C`armv8.4\-a\*(C'\fR \*(C`armv8.5\-a\*(C'\fR, \f(CW\*(C`armv8.6\-a\*(C'\fR, \f(CW\*(C`armv8.7\-a\*(C'\fR, \f(CW\*(C`armv8.8\-a\*(C'\fR, \*(C`armv8\-r\*(C'\fR, \f(CW\*(C`armv9\-a\*(C'\fR, \f(CW\*(C`armv9.1\-a\*(C'\fR, \f(CW\*(C`armv9.2\-a\*(C'\fR, and \*(C`armv9.3\-a\*(C'\fR. If both −mcpu and −march are specified, the assembler will use the setting for −mcpu. If neither are specified, the assembler will default to −mcpu=all. The architecture option can be extended with the same instruction set extension options as the −mcpu option. Unlike −mcpu, extensions are not always enabled by default, −mverbose−error This option enables verbose error messages for AArch64 gas. This option is enabled by default. −mno−verbose−error This option disables verbose error messages in AArch64 gas. The following options are available when as is configured for an Alpha processor. −mcpu This option specifies the target processor. If an attempt is made to assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. This option is equivalent to the \*(C`.arch\*(C'\fR directive. The following processor names are recognized: 21064, \*(C`21064a\*(C'\fR, 21066, 21068, 21164, \*(C`21164a\*(C'\fR, \*(C`21164pc\*(C'\fR, 21264, \*(C`21264a\*(C'\fR, \*(C`21264b\*(C'\fR, \*(C`ev4\*(C'\fR, \*(C`ev5\*(C'\fR, \*(C`lca45\*(C'\fR, \*(C`ev5\*(C'\fR, \*(C`ev56\*(C'\fR, \*(C`pca56\*(C'\fR, \*(C`ev6\*(C'\fR, \*(C`ev67\*(C'\fR, \*(C`ev68\*(C'\fR. The special name \*(C`all\*(C'\fR may be used to allow the assembler to accept instructions valid for any Alpha processor. In order to support existing practice in OSF/1 with respect to \*(C`.arch\*(C'\fR, and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the "electro-vlasic" names (e.g. \*(C`ev4\*(C'\fR) do not. −mdebug −no−mdebug Enables or disables the generation of \*(C`.mdebug\*(C'\fR encapsulation for stabs directives and procedure descriptors. The default is to automatically enable \*(C`.mdebug\*(C'\fR when the first stabs directive is seen. −relax This option forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. Note that this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. However, the option can still be useful in specific applications. −replace −noreplace Enables or disables the optimization of procedure calls, both at assemblage and at link time. These options are only available for VMS targets and \*(C`\-replace\*(C'\fR is the default. See section 1.4.1 of the OpenVMS Linker Utility Manual. −g This option is used when the compiler generates debug information. When gcc is using mips-tfile to generate debug information for ECOFF, local labels must be passed through to the object file. Otherwise this option has no effect. −Gsize A local common symbol larger than size is placed in \*(C`.bss\*(C'\fR, while smaller symbols are placed in \*(C`.sbss\*(C'\fR. −F −32addr These options are ignored for backward compatibility. The following options are available when as is configured for an ARC processor. −mcpu=cpu This option selects the core processor variant. −EB | −EL Select either big-endian (−EB) or little-endian (−EL) output. −mcode−density Enable Code Density extension instructions. The following options are available when as is configured for the ARM processor family. −mcpu=processor[+extension...] Specify which ARM processor variant is the target. −march=architecture[+extension...] Specify which ARM architecture variant is used by the target. −mfpu=floating-point-format Select which Floating Point architecture is the target. −mfloat−abi=abi Select which floating point ABI is in use. −mthumb Enable Thumb only instruction decoding. −mapcs−32 | −mapcs−26 | −mapcs−float | −mapcs−reentrant Select which procedure calling convention is in use. −EB | −EL Select either big-endian (−EB) or little-endian (−EL) output. −mthumb−interwork Specify that the code has been generated with interworking between Thumb and ARM code in mind. −mccs Turns on CodeComposer Studio assembly syntax compatibility mode. −k Specify that PIC code has been generated. The following options are available when as is configured for the Blackfin processor family. −mcpu=processor[−sirevision] This option specifies the target processor. The optional sirevision is not used in assembler. It's here such that GCC can easily pass down its \*(C`\-mcpu=\*(C'\fR option. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: \*(C`bf504\*(C'\fR, \*(C`bf506\*(C'\fR, \*(C`bf512\*(C'\fR, \*(C`bf514\*(C'\fR, \*(C`bf516\*(C'\fR, \*(C`bf518\*(C'\fR, \*(C`bf522\*(C'\fR, \*(C`bf523\*(C'\fR, \*(C`bf524\*(C'\fR, \*(C`bf525\*(C'\fR, \*(C`bf526\*(C'\fR, \*(C`bf527\*(C'\fR, \*(C`bf531\*(C'\fR, \*(C`bf532\*(C'\fR, \*(C`bf533\*(C'\fR, \*(C`bf534\*(C'\fR, \*(C`bf535\*(C'\fR (not implemented yet), \*(C`bf536\*(C'\fR, \*(C`bf537\*(C'\fR, \*(C`bf538\*(C'\fR, \*(C`bf539\*(C'\fR, \*(C`bf542\*(C'\fR, \*(C`bf542m\*(C'\fR, \*(C`bf544\*(C'\fR, \*(C`bf544m\*(C'\fR, \*(C`bf547\*(C'\fR, \*(C`bf547m\*(C'\fR, \*(C`bf548\*(C'\fR, \*(C`bf548m\*(C'\fR, \*(C`bf549\*(C'\fR, \*(C`bf549m\*(C'\fR, \*(C`bf561\*(C'\fR, and \*(C`bf592\*(C'\fR. −mfdpic Assemble for the FDPIC ABI. −mno−fdpic −mnopic Disable −mfdpic. The following options are available when as is configured for the Linux kernel BPF processor family. @chapter BPF Dependent Features
Options−EB This option specifies that the assembler should emit big-endian eBPF. −EL This option specifies that the assembler should emit little-endian eBPF. Note that if no endianness option is specified in the command line, the host endianness is used. See the info pages for documentation of the CRIS-specific options. The following options are available when as is configured for the C−SKY processor family. −march=archname Assemble for architecture archname. The −−help option lists valid values for archname. −mcpu=cpuname Assemble for architecture cpuname. The −−help option lists valid values for cpuname. −EL −mlittle−endian Generate little-endian output. −EB −mbig−endian Generate big-endian output. −fpic −pic Generate position-independent code. −mljump −mno−ljump Enable/disable transformation of the short branch instructions \*(C`jbf\*(C'\fR, \f(CW\*(C`jbt\*(C'\fR, and \f(CW\*(C`jbr\*(C'\fR to \f(CW\*(C`jmpi\*(C'\fR. This option is for V2 processors only. It is ignored on CK801 and CK802 targets, which do not support the \*(C`jmpi\*(C'\fR instruction, and is enabled by default for other processors. −mbranch−stub −mno−branch−stub Pass through \*(C`R_CKCORE_PCREL_IMM26BY2\*(C'\fR relocations for \f(CW\*(C`bsr\*(C'\fR instructions to the linker. This option is only available for bare-metal C−SKY V2 ELF targets, where it is enabled by default. It cannot be used in code that will be dynamically linked against shared libraries. −force2bsr −mforce2bsr −no−force2bsr −mno−force2bsr Enable/disable transformation of \*(C`jbsr\*(C'\fR instructions to \f(CW\*(C`bsr\*(C'\fR. This option is always enabled (and −mno−force2bsr is ignored) for CK801/CK802 targets. It is also always enabled when −mbranch−stub is in effect. −jsri2bsr −mjsri2bsr −no−jsri2bsr −mno−jsri2bsr Enable/disable transformation of \*(C`jsri\*(C'\fR instructions to \f(CW\*(C`bsr\*(C'\fR. This option is enabled by default. −mnolrw −mno−lrw Enable/disable transformation of \*(C`lrw\*(C'\fR instructions into a \*(C`movih\*(C'\fR/\f(CW\*(C`ori\*(C'\fR pair. −melrw −mno−elrw Enable/disable extended \*(C`lrw\*(C'\fR instructions. This option is enabled by default for CK800−series processors. −mlaf −mliterals−after−func −mno−laf −mno−literals−after−func Enable/disable placement of literal pools after each function. −mlabr −mliterals−after−br −mno−labr −mnoliterals−after−br Enable/disable placement of literal pools after unconditional branches. This option is enabled by default. −mistack −mno−istack Enable/disable interrupt stack instructions. This option is enabled by default on CK801, CK802, and CK802 processors. The following options explicitly enable certain optional instructions. These features are also enabled implicitly by using \*(C`\-mcpu=\*(C'\fR to specify a processor that supports it. −mhard−float Enable hard float instructions. −mmp Enable multiprocessor instructions. −mcp Enable coprocessor instructions. −mcache Enable cache prefetch instruction. −msecurity Enable C−SKY security instructions. −mtrust Enable C−SKY trust instructions. −mdsp Enable DSP instructions. −medsp Enable enhanced DSP instructions. −mvdsp Enable vector DSP instructions. The following options are available when as is configured for an Epiphany processor. −mepiphany Specifies that the both 32 and 16 bit instructions are allowed. This is the default behavior. −mepiphany16 Restricts the permitted instructions to just the 16 bit set. The following options are available when as is configured for an H8/300 processor. @chapter H8/300 Dependent Features
OptionsThe Renesas H8/300 version of \*(C`as\*(C'\fR has one machine-dependent option: −h−tick−hex Support H'00 style hex constants in addition to 0x00 style. −mach=name Sets the H8300 machine variant. The following machine names are recognised: \*(C`h8300h\*(C'\fR, \*(C`h8300hn\*(C'\fR, \*(C`h8300s\*(C'\fR, \*(C`h8300sn\*(C'\fR, \*(C`h8300sx\*(C'\fR and \*(C`h8300sxn\*(C'\fR. The following options are available when as is configured for an i386 processor. −−32 | −−x32 | −−64 Select the word size, either 32 bits or 64 bits. −−32 implies Intel i386 architecture, while −−x32 and −−64 imply AMD x86−64 architecture with 32−bit or 64−bit word-size respectively. These options are only available with the ELF object file format, and require that the necessary BFD support has been included (on a 32−bit platform you have to add −−enable−64−bit−bfd to configure enable 64−bit usage and use x86−64 as target platform). −n By default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. This switch disables the optimization if a single byte nop (0x90) is explicitly specified as the fill byte for alignment. −−divide On SVR4−derived platforms, the character / is treated as a comment character, which means that it cannot be used in expressions. The −−divide option turns / into a normal character. This does not disable / at the beginning of a line starting a comment, or affect using # for starting a comment. −march=CPU[+EXTENSION...] This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: \*(C`i8086\*(C'\fR, \*(C`i186\*(C'\fR, \*(C`i286\*(C'\fR, \*(C`i386\*(C'\fR, \*(C`i486\*(C'\fR, \*(C`i586\*(C'\fR, \*(C`i686\*(C'\fR, \*(C`pentium\*(C'\fR, \*(C`pentiumpro\*(C'\fR, \*(C`pentiumii\*(C'\fR, \*(C`pentiumiii\*(C'\fR, \*(C`pentium4\*(C'\fR, \*(C`prescott\*(C'\fR, \*(C`nocona\*(C'\fR, \*(C`core\*(C'\fR, \*(C`core2\*(C'\fR, \*(C`corei7\*(C'\fR, \*(C`iamcu\*(C'\fR, \*(C`k6\*(C'\fR, \*(C`k6_2\*(C'\fR, \*(C`athlon\*(C'\fR, \*(C`opteron\*(C'\fR, \*(C`k8\*(C'\fR, \*(C`amdfam10\*(C'\fR, \*(C`bdver1\*(C'\fR, \*(C`bdver2\*(C'\fR, \*(C`bdver3\*(C'\fR, \*(C`bdver4\*(C'\fR, \*(C`znver1\*(C'\fR, \*(C`znver2\*(C'\fR, \*(C`znver3\*(C'\fR, \*(C`btver1\*(C'\fR, \*(C`btver2\*(C'\fR, \*(C`generic32\*(C'\fR and \*(C`generic64\*(C'\fR. In addition to the basic instruction set, the assembler can be told to accept various extension mnemonics. For example, \*(C`\-march=i686+sse4+vmx\*(C'\fR extends \fIi686\fR with \fIsse4\fR and vmx. The following extensions are currently supported: 8087, 287, 387, 687, \*(C`no87\*(C'\fR, \*(C`no287\*(C'\fR, \*(C`no387\*(C'\fR, \*(C`no687\*(C'\fR, \*(C`cmov\*(C'\fR, \*(C`nocmov\*(C'\fR, \*(C`fxsr\*(C'\fR, \*(C`nofxsr\*(C'\fR, \*(C`mmx\*(C'\fR, \*(C`nommx\*(C'\fR, \*(C`sse\*(C'\fR, \*(C`sse2\*(C'\fR, \*(C`sse3\*(C'\fR, \*(C`sse4a\*(C'\fR, \*(C`ssse3\*(C'\fR, \*(C`sse4.1\*(C'\fR, \*(C`sse4.2\*(C'\fR, \*(C`sse4\*(C'\fR, \*(C`nosse\*(C'\fR, \*(C`nosse2\*(C'\fR, \*(C`nosse3\*(C'\fR, \*(C`nosse4a\*(C'\fR, \*(C`nossse3\*(C'\fR, \*(C`nosse4.1\*(C'\fR, \*(C`nosse4.2\*(C'\fR, \*(C`nosse4\*(C'\fR, \*(C`avx\*(C'\fR, \*(C`avx2\*(C'\fR, \*(C`noavx\*(C'\fR, \*(C`noavx2\*(C'\fR, \*(C`adx\*(C'\fR, \*(C`rdseed\*(C'\fR, \*(C`prfchw\*(C'\fR, \*(C`smap\*(C'\fR, \*(C`mpx\*(C'\fR, \*(C`sha\*(C'\fR, \*(C`rdpid\*(C'\fR, \*(C`ptwrite\*(C'\fR, \*(C`cet\*(C'\fR, \*(C`gfni\*(C'\fR, \*(C`vaes\*(C'\fR, \*(C`vpclmulqdq\*(C'\fR, \*(C`prefetchwt1\*(C'\fR, \*(C`clflushopt\*(C'\fR, \*(C`se1\*(C'\fR, \*(C`clwb\*(C'\fR, \*(C`movdiri\*(C'\fR, \*(C`movdir64b\*(C'\fR, \*(C`enqcmd\*(C'\fR, \*(C`serialize\*(C'\fR, \*(C`tsxldtrk\*(C'\fR, \*(C`kl\*(C'\fR, \*(C`nokl\*(C'\fR, \*(C`widekl\*(C'\fR, \*(C`nowidekl\*(C'\fR, \*(C`hreset\*(C'\fR, \*(C`avx512f\*(C'\fR, \*(C`avx512cd\*(C'\fR, \*(C`avx512er\*(C'\fR, \*(C`avx512pf\*(C'\fR, \*(C`avx512vl\*(C'\fR, \*(C`avx512bw\*(C'\fR, \*(C`avx512dq\*(C'\fR, \*(C`avx512ifma\*(C'\fR, \*(C`avx512vbmi\*(C'\fR, \*(C`avx512_4fmaps\*(C'\fR, \*(C`avx512_4vnniw\*(C'\fR, \*(C`avx512_vpopcntdq\*(C'\fR, \*(C`avx512_vbmi2\*(C'\fR, \*(C`avx512_vnni\*(C'\fR, \*(C`avx512_bitalg\*(C'\fR, \*(C`avx512_vp2intersect\*(C'\fR, \*(C`tdx\*(C'\fR, \*(C`avx512_bf16\*(C'\fR, \*(C`avx_vnni\*(C'\fR, \*(C`avx512_fp16\*(C'\fR, \*(C`noavx512f\*(C'\fR, \*(C`noavx512cd\*(C'\fR, \*(C`noavx512er\*(C'\fR, \*(C`noavx512pf\*(C'\fR, \*(C`noavx512vl\*(C'\fR, \*(C`noavx512bw\*(C'\fR, \*(C`noavx512dq\*(C'\fR, \*(C`noavx512ifma\*(C'\fR, \*(C`noavx512vbmi\*(C'\fR, \*(C`noavx512_4fmaps\*(C'\fR, \*(C`noavx512_4vnniw\*(C'\fR, \*(C`noavx512_vpopcntdq\*(C'\fR, \*(C`noavx512_vbmi2\*(C'\fR, \*(C`noavx512_vnni\*(C'\fR, \*(C`noavx512_bitalg\*(C'\fR, \*(C`noavx512_vp2intersect\*(C'\fR, \*(C`notdx\*(C'\fR, \*(C`noavx512_bf16\*(C'\fR, \*(C`noavx_vnni\*(C'\fR, \*(C`noavx512_fp16\*(C'\fR, \*(C`noenqcmd\*(C'\fR, \*(C`noserialize\*(C'\fR, \*(C`notsxldtrk\*(C'\fR, \*(C`amx_int8\*(C'\fR, \*(C`noamx_int8\*(C'\fR, \*(C`amx_bf16\*(C'\fR, \*(C`noamx_bf16\*(C'\fR, \*(C`amx_tile\*(C'\fR, \*(C`noamx_tile\*(C'\fR, \*(C`nouintr\*(C'\fR, \*(C`nohreset\*(C'\fR, \*(C`vmx\*(C'\fR, \*(C`vmfunc\*(C'\fR, \*(C`smx\*(C'\fR, \*(C`xsave\*(C'\fR, \*(C`xsaveopt\*(C'\fR, \*(C`xsavec\*(C'\fR, \*(C`xsaves\*(C'\fR, \*(C`aes\*(C'\fR, \*(C`pclmul\*(C'\fR, \*(C`fsgsbase\*(C'\fR, \*(C`rdrnd\*(C'\fR, \*(C`f16c\*(C'\fR, \*(C`bmi2\*(C'\fR, \*(C`fma\*(C'\fR, \*(C`movbe\*(C'\fR, \*(C`ept\*(C'\fR, \*(C`lzcnt\*(C'\fR, \*(C`popcnt\*(C'\fR, \*(C`hle\*(C'\fR, \*(C`rtm\*(C'\fR, \*(C`invpcid\*(C'\fR, \*(C`clflush\*(C'\fR, \*(C`mwaitx\*(C'\fR, \*(C`clzero\*(C'\fR, \*(C`wbnoinvd\*(C'\fR, \*(C`pconfig\*(C'\fR, \*(C`waitpkg\*(C'\fR, \*(C`uintr\*(C'\fR, \*(C`cldemote\*(C'\fR, \*(C`rdpru\*(C'\fR, \*(C`mcommit\*(C'\fR, \*(C`sev_es\*(C'\fR, \*(C`lwp\*(C'\fR, \*(C`fma4\*(C'\fR, \*(C`xop\*(C'\fR, \*(C`cx16\*(C'\fR, \*(C`syscall\*(C'\fR, \*(C`rdtscp\*(C'\fR, \*(C`3dnow\*(C'\fR, \*(C`3dnowa\*(C'\fR, \*(C`sse4a\*(C'\fR, \*(C`sse5\*(C'\fR, \*(C`snp\*(C'\fR, \*(C`invlpgb\*(C'\fR, \*(C`tlbsync\*(C'\fR, \*(C`svme\*(C'\fR and \*(C`padlock\*(C'\fR. Note that rather than extending a basic instruction set, the extension mnemonics starting with \*(C`no\*(C'\fR revoke the respective functionality. When the \*(C`.arch\*(C'\fR directive is used with \fB\-march\fR, the \*(C`.arch\*(C'\fR directive will take precedent. −mtune=CPU This option specifies a processor to optimize for. When used in conjunction with the −march option, only instructions of the processor specified by the −march option will be generated. Valid CPU values are identical to the processor list of −march=CPU. −msse2avx This option specifies that the assembler should encode SSE instructions with VEX prefix. −muse−unaligned−vector−move This option specifies that the assembler should encode aligned vector move as unaligned vector move. −msse−check=none −msse−check=warning −msse−check=error These options control if the assembler should check SSE instructions. −msse−check=none will make the assembler not to check SSE instructions, which is the default. −msse−check=warning will make the assembler issue a warning for any SSE instruction. −msse−check=error will make the assembler issue an error for any SSE instruction. −mavxscalar=128 −mavxscalar=256 These options control how the assembler should encode scalar AVX instructions. −mavxscalar=128 will encode scalar AVX instructions with 128bit vector length, which is the default. −mavxscalar=256 will encode scalar AVX instructions with 256bit vector length. WARNING: Don't use this for production code − due to CPU errata the resulting code may not work on certain models. −mvexwig=0 −mvexwig=1 These options control how the assembler should encode VEX.W−ignored (WIG) VEX instructions. −mvexwig=0 will encode WIG VEX instructions with vex.w = 0, which is the default. −mvexwig=1 will encode WIG EVEX instructions with vex.w = 1. WARNING: Don't use this for production code − due to CPU errata the resulting code may not work on certain models. −mevexlig=128 −mevexlig=256 −mevexlig=512 These options control how the assembler should encode length-ignored (LIG) EVEX instructions. −mevexlig=128 will encode LIG EVEX instructions with 128bit vector length, which is the default. −mevexlig=256 and −mevexlig=512 will encode LIG EVEX instructions with 256bit and 512bit vector length, respectively. −mevexwig=0 −mevexwig=1 These options control how the assembler should encode w−ignored (WIG) EVEX instructions. −mevexwig=0 will encode WIG EVEX instructions with evex.w = 0, which is the default. −mevexwig=1 will encode WIG EVEX instructions with evex.w = 1. −mmnemonic=att −mmnemonic=intel This option specifies instruction mnemonic for matching instructions. The \*(C`.att_mnemonic\*(C'\fR and \f(CW\*(C`.intel_mnemonic\*(C'\fR directives will take precedent. −msyntax=att −msyntax=intel This option specifies instruction syntax when processing instructions. The \*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR directives will take precedent. −mnaked−reg This option specifies that registers don't require a % prefix. The \*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR directives will take precedent. −madd−bnd−prefix This option forces the assembler to add BND prefix to all branches, even if such prefix was not explicitly specified in the source code. −mno−shared On ELF target, the assembler normally optimizes out non-PLT relocations against defined non-weak global branch targets with default visibility. The −mshared option tells the assembler to generate code which may go into a shared library where all non-weak global branch targets with default visibility can be preempted. The resulting code is slightly bigger. This option only affects the handling of branch instructions. −mbig−obj On PE/COFF target this option forces the use of big object file format, which allows more than 32768 sections. −momit−lock−prefix=no −momit−lock−prefix=yes These options control how the assembler should encode lock prefix. This option is intended as a workaround for processors, that fail on lock prefix. This option can only be safely used with single-core, single-thread computers −momit−lock−prefix=yes will omit all lock prefixes. −momit−lock−prefix=no will encode lock prefix as usual, which is the default. −mfence−as−lock−add=no −mfence−as−lock−add=yes These options control how the assembler should encode lfence, mfence and sfence. −mfence−as−lock−add=yes will encode lfence, mfence and sfence as lock addl $0x0, (%rsp) in 64−bit mode and lock addl $0x0, (%esp) in 32−bit mode. −mfence−as−lock−add=no will encode lfence, mfence and sfence as usual, which is the default. −mrelax−relocations=no −mrelax−relocations=yes These options control whether the assembler should generate relax relocations, R_386_GOT32X, in 32−bit mode, or R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX, in 64−bit mode. −mrelax−relocations=yes will generate relax relocations. −mrelax−relocations=no will not generate relax relocations. The default can be controlled by a configure option −−enable−x86−relax−relocations. −malign−branch−boundary=NUM This option controls how the assembler should align branches with segment prefixes or NOP. NUM must be a power of 2. It should be 0 or no less than 16. Branches will be aligned within NUM byte boundary. −malign−branch−boundary=0, which is the default, doesn't align branches. −malign−branch=TYPE[+TYPE...] This option specifies types of branches to align. TYPE is combination of jcc, which aligns conditional jumps, fused, which aligns fused conditional jumps, jmp, which aligns unconditional jumps, call which aligns calls, ret, which aligns rets, indirect, which aligns indirect jumps and calls. The default is −malign−branch=jcc+fused+jmp. −malign−branch−prefix−size=NUM This option specifies the maximum number of prefixes on an instruction to align branches. NUM should be between 0 and 5. The default NUM is 5. −mbranches−within−32B−boundaries This option aligns conditional jumps, fused conditional jumps and unconditional jumps within 32 byte boundary with up to 5 segment prefixes on an instruction. It is equivalent to −malign−branch−boundary=32 −malign−branch=jcc+fused+jmp −malign−branch−prefix−size=5. The default doesn't align branches. −mlfence−after−load=no −mlfence−after−load=yes These options control whether the assembler should generate lfence after load instructions. −mlfence−after−load=yes will generate lfence. −mlfence−after−load=no will not generate lfence, which is the default. −mlfence−before−indirect−branch=none −mlfence−before−indirect−branch=all −mlfence−before−indirect−branch=register −mlfence−before−indirect−branch=memory These options control whether the assembler should generate lfence before indirect near branch instructions. −mlfence−before−indirect−branch=all will generate lfence before indirect near branch via register and issue a warning before indirect near branch via memory. It also implicitly sets −mlfence−before−ret=shl when there's no explicit −mlfence−before−ret=. −mlfence−before−indirect−branch=register will generate lfence before indirect near branch via register. −mlfence−before−indirect−branch=memory will issue a warning before indirect near branch via memory. −mlfence−before−indirect−branch=none will not generate lfence nor issue warning, which is the default. Note that lfence won't be generated before indirect near branch via register with −mlfence−after−load=yes since lfence will be generated after loading branch target register. −mlfence−before−ret=none −mlfence−before−ret=shl −mlfence−before−ret=or −mlfence−before−ret=yes −mlfence−before−ret=not These options control whether the assembler should generate lfence before ret. −mlfence−before−ret=or will generate generate or instruction with lfence. −mlfence−before−ret=shl/yes will generate shl instruction with lfence. −mlfence−before−ret=not will generate not instruction with lfence. −mlfence−before−ret=none will not generate lfence, which is the default. −mx86−used−note=no −mx86−used−note=yes These options control whether the assembler should generate GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU property notes. The default can be controlled by the −−enable−x86−used−note configure option. −mevexrcig=rne −mevexrcig=rd −mevexrcig=ru −mevexrcig=rz These options control how the assembler should encode SAE-only EVEX instructions. −mevexrcig=rne will encode RC bits of EVEX instruction with 00, which is the default. −mevexrcig=rd, −mevexrcig=ru and −mevexrcig=rz will encode SAE-only EVEX instructions with 01, 10 and 11 RC bits, respectively. −mamd64 −mintel64 This option specifies that the assembler should accept only AMD64 or Intel64 ISA in 64−bit mode. The default is to accept common, Intel64 only and AMD64 ISAs. −O0 | −O | −O1 | −O2 | −Os Optimize instruction encoding with smaller instruction size. −O and −O1 encode 64−bit register load instructions with 64−bit immediate as 32−bit register load instructions with 31−bit or 32−bits immediates, encode 64−bit register clearing instructions with 32−bit register clearing instructions, encode 256−bit/512−bit VEX/EVEX vector register clearing instructions with 128−bit VEX vector register clearing instructions, encode 128−bit/256−bit EVEX vector register load/store instructions with VEX vector register load/store instructions, and encode 128−bit/256−bit EVEX packed integer logical instructions with 128−bit/256−bit VEX packed integer logical. −O2 includes −O1 optimization plus encodes 256−bit/512−bit EVEX vector register clearing instructions with 128−bit EVEX vector register clearing instructions. In 64−bit mode VEX encoded instructions with commutative source operands will also have their source operands swapped if this allows using the 2−byte VEX prefix form instead of the 3−byte one. Certain forms of AND as well as OR with the same (register) operand specified twice will also be changed to TEST. −Os includes −O2 optimization plus encodes 16−bit, 32−bit and 64−bit register tests with immediate as 8−bit register test with immediate. −O0 turns off this optimization. The following options are available when as is configured for the Ubicom IP2K series. −mip2022ext Specifies that the extended IP2022 instructions are allowed. −mip2022 Restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones. The following options are available when as is configured for the Renesas M32C and M16C processors. −m32c Assemble M32C instructions. −m16c Assemble M16C instructions (the default). −relax Enable support for link-time relaxations. −h−tick−hex Support H'00 style hex constants in addition to 0x00 style. The following options are available when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series. −−m32rx Specify which processor in the M32R family is the target. The default is normally the M32R, but this option changes it to the M32RX. −−warn−explicit−parallel−conflicts or −−Wp Produce warning messages when questionable parallel constructs are encountered. −−no−warn−explicit−parallel−conflicts or −−Wnp Do not produce warning messages when questionable parallel constructs are encountered. The following options are available when as is configured for the Motorola 68000 series. −l Shorten references to undefined symbols, to one word instead of two. −m68000 | −m68008 | −m68010 | −m68020 | −m68030 | −m68040 | −m68060 | −m68302 | −m68331 | −m68332 | −m68333 | −m68340 | −mcpu32 | −m5200 Specify what processor in the 68000 family is the target. The default is normally the 68020, but this can be changed at configuration time. −m68881 | −m68882 | −mno−68881 | −mno−68882 The target machine does (or does not) have a floating-point coprocessor. The default is to assume a coprocessor for 68020, 68030, and cpu32. Although the basic 68000 is not compatible with the 68881, a combination of the two can be specified, since it's possible to do emulation of the coprocessor instructions with the main processor. −m68851 | −mno−68851 The target machine does (or does not) have a memory-management unit coprocessor. The default is to assume an MMU for 68020 and up. The following options are available when as is configured for an Altera Nios II processor. −relax−section Replace identified out-of-range branches with PC-relative \*(C`jmp\*(C'\fR sequences when possible. The generated code sequences are suitable for use in position-independent code, but there is a practical limit on the extended branch range because of the length of the sequences. This option is the default. −relax−all Replace branch instructions not determinable to be in range and all call instructions with \*(C`jmp\*(C'\fR and \f(CW\*(C`callr\*(C'\fR sequences (respectively). This option generates absolute relocations against the target symbols and is not appropriate for position-independent code. −no−relax Do not replace any branches or calls. −EB Generate big-endian output. −EL Generate little-endian output. This is the default. −march=architecture This option specifies the target architecture. The assembler issues an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. The following architecture names are recognized: \*(C`r1\*(C'\fR, \*(C`r2\*(C'\fR. The default is \*(C`r1\*(C'\fR. The following options are available when as is configured for a PRU processor. −mlink−relax Assume that LD would optimize LDI32 instructions by checking the upper 16 bits of the expression. If they are all zeros, then LD would shorten the LDI32 instruction to a single LDI. In such case \*(C`as\*(C'\fR will output DIFF relocations for diff expressions. −mno−link−relax Assume that LD would not optimize LDI32 instructions. As a consequence, DIFF relocations will not be emitted. −mno−warn−regname−label Do not warn if a label name matches a register name. Usually assembler programmers will want this warning to be emitted. C compilers may want to turn this off. The following options are available when as is configured for a MIPS processor. −G num This option sets the largest size of an object that can be referenced implicitly with the \*(C`gp\*(C'\fR register. It is only accepted for targets that use ECOFF format, such as a DECstation running Ultrix. The default value is 8. −EB Generate "big endian" format output. −EL Generate "little endian" format output. −mips1 −mips2 −mips3 −mips4 −mips5 −mips32 −mips32r2 −mips32r3 −mips32r5 −mips32r6 −mips64 −mips64r2 −mips64r3 −mips64r5 −mips64r6 Generate code for a particular MIPS Instruction Set Architecture level. −mips1 is an alias for −march=r3000, −mips2 is an alias for −march=r6000, −mips3 is an alias for −march=r4000 and −mips4 is an alias for −march=r8000. −mips5, −mips32, −mips32r2, −mips32r3, −mips32r5, −mips32r6, −mips64, −mips64r2, −mips64r3, −mips64r5, and −mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, respectively. −march=cpu Generate code for a particular MIPS CPU. −mtune=cpu Schedule and tune for a particular MIPS CPU. −mfix7000 −mno−fix7000 Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions. −mfix−rm7000 −mno−fix−rm7000 Cause nops to be inserted if a dmult or dmultu instruction is followed by a load instruction. −mfix−r5900 −mno−fix−r5900 Do not attempt to schedule the preceding instruction into the delay slot of a branch instruction placed at the end of a short loop of six instructions or fewer and always schedule a \*(C`nop\*(C'\fR instruction there instead. The short loop bug under certain conditions causes loops to execute only once or twice, due to a hardware bug in the R5900 chip. −mdebug −no−mdebug Cause stabs-style debugging output to go into an ECOFF-style .mdebug section instead of the standard ELF .stabs sections. −mpdr −mno−pdr Control generation of \*(C`.pdr\*(C'\fR sections. −mgp32 −mfp32 The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. −mgp32 controls the size of general-purpose registers and −mfp32 controls the size of floating-point registers. −mgp64 −mfp64 The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 64 bits wide at all times. −mgp64 controls the size of general-purpose registers and −mfp64 controls the size of floating-point registers. −mfpxx The register sizes are normally inferred from the ISA and ABI, but using this flag in combination with −mabi=32 enables an ABI variant which will operate correctly with floating-point registers which are 32 or 64 bits wide. −modd−spreg −mno−odd−spreg Enable use of floating-point operations on odd-numbered single-precision registers when supported by the ISA. −mfpxx implies −mno−odd−spreg, otherwise the default is −modd−spreg. −mips16 −no−mips16 Generate code for the MIPS 16 processor. This is equivalent to putting \*(C`.module mips16\*(C'\fR at the start of the assembly file. \fB\-no\-mips16\fR turns off this option. −mmips16e2 −mno−mips16e2 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent to putting \*(C`.module mips16e2\*(C'\fR at the start of the assembly file. −mno−mips16e2 turns off this option. −mmicromips −mno−micromips Generate code for the microMIPS processor. This is equivalent to putting \*(C`.module micromips\*(C'\fR at the start of the assembly file. −mno−micromips turns off this option. This is equivalent to putting \*(C`.module nomicromips\*(C'\fR at the start of the assembly file. −msmartmips −mno−smartmips Enables the SmartMIPS extension to the MIPS32 instruction set. This is equivalent to putting \*(C`.module smartmips\*(C'\fR at the start of the assembly file. −mno−smartmips turns off this option. −mips3d −no−mips3d Generate code for the MIPS−3D Application Specific Extension. This tells the assembler to accept MIPS−3D instructions. −no−mips3d turns off this option. −mdmx −no−mdmx Generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. −no−mdmx turns off this option. −mdsp −mno−dsp Generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions. −mno−dsp turns off this option. −mdspr2 −mno−dspr2 Generate code for the DSP Release 2 Application Specific Extension. This option implies −mdsp. This tells the assembler to accept DSP Release 2 instructions. −mno−dspr2 turns off this option. −mdspr3 −mno−dspr3 Generate code for the DSP Release 3 Application Specific Extension. This option implies −mdsp and −mdspr2. This tells the assembler to accept DSP Release 3 instructions. −mno−dspr3 turns off this option. −mmsa −mno−msa Generate code for the MIPS SIMD Architecture Extension. This tells the assembler to accept MSA instructions. −mno−msa turns off this option. −mxpa −mno−xpa Generate code for the MIPS eXtended Physical Address (XPA) Extension. This tells the assembler to accept XPA instructions. −mno−xpa turns off this option. −mmt −mno−mt Generate code for the MT Application Specific Extension. This tells the assembler to accept MT instructions. −mno−mt turns off this option. −mmcu −mno−mcu Generate code for the MCU Application Specific Extension. This tells the assembler to accept MCU instructions. −mno−mcu turns off this option. −mcrc −mno−crc Generate code for the MIPS cyclic redundancy check (CRC) Application Specific Extension. This tells the assembler to accept CRC instructions. −mno−crc turns off this option. −mginv −mno−ginv Generate code for the Global INValidate (GINV) Application Specific Extension. This tells the assembler to accept GINV instructions. −mno−ginv turns off this option. −mloongson−mmi −mno−loongson−mmi Generate code for the Loongson MultiMedia extensions Instructions (MMI) Application Specific Extension. This tells the assembler to accept MMI instructions. −mno−loongson−mmi turns off this option. −mloongson−cam −mno−loongson−cam Generate code for the Loongson Content Address Memory (CAM) instructions. This tells the assembler to accept Loongson CAM instructions. −mno−loongson−cam turns off this option. −mloongson−ext −mno−loongson−ext Generate code for the Loongson EXTensions (EXT) instructions. This tells the assembler to accept Loongson EXT instructions. −mno−loongson−ext turns off this option. −mloongson−ext2 −mno−loongson−ext2 Generate code for the Loongson EXTensions R2 (EXT2) instructions. This option implies −mloongson−ext. This tells the assembler to accept Loongson EXT2 instructions. −mno−loongson−ext2 turns off this option. −minsn32 −mno−insn32 Only use 32−bit instruction encodings when generating code for the microMIPS processor. This option inhibits the use of any 16−bit instructions. This is equivalent to putting \*(C`.set insn32\*(C'\fR at the start of the assembly file. −mno−insn32 turns off this option. This is equivalent to putting \*(C`.set noinsn32\*(C'\fR at the start of the assembly file. By default −mno−insn32 is selected, allowing all instructions to be used. −−construct−floats −−no−construct−floats The −−no−construct−floats option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. By default −−construct−floats is selected, allowing construction of these floating point constants. −−relax−branch −−no−relax−branch The −−relax−branch option enables the relaxation of out-of-range branches. By default −−no−relax−branch is selected, causing any out-of-range branches to produce an error. −mignore−branch−isa −mno−ignore−branch−isa Ignore branch checks for invalid transitions between ISA modes. The semantics of branches does not provide for an ISA mode switch, so in most cases the ISA mode a branch has been encoded for has to be the same as the ISA mode of the branch's target label. Therefore GAS has checks implemented that verify in branch assembly that the two ISA modes match. −mignore−branch−isa disables these checks. By default −mno−ignore−branch−isa is selected, causing any invalid branch requiring a transition between ISA modes to produce an error. −mnan=encoding Select between the IEEE 754−2008 (−mnan=2008) or the legacy (−mnan=legacy) NaN encoding format. The latter is the default. −−emulation=name This option was formerly used to switch between ELF and ECOFF output on targets like IRIX 5 that supported both. MIPS ECOFF support was removed in GAS 2.24, so the option now serves little purpose. It is retained for backwards compatibility. The available configuration names are: mipself, mipslelf and mipsbelf. Choosing mipself now has no effect, since the output is always ELF. mipslelf and mipsbelf select little− and big-endian output respectively, but −EL and −EB are now the preferred options instead. −nocpp as ignores this option. It is accepted for compatibility with the native tools. −−trap −−no−trap −−break −−no−break Control how to deal with multiplication overflow and division by zero. −−trap or −−no−break (which are synonyms) take a trap exception (and only work for Instruction Set Architecture level 2 and higher); −−break or −−no−trap (also synonyms, and the default) take a break exception. −n When this option is used, as will issue a warning every time it generates a nop instruction from a macro. The following options are available when as is configured for a LoongArch processor. −fpic −fPIC Generate position-independent code −fno−pic Don't generate position-independent code (default) The following options are available when as is configured for a Meta processor. −mcpu=metac11 Generate code for Meta 1.1. −mcpu=metac12 Generate code for Meta 1.2. −mcpu=metac21 Generate code for Meta 2.1. −mfpu=metac21 Allow code to use FPU hardware of Meta 2.1. See the info pages for documentation of the MMIX-specific options. The following options are available when as is configured for a NDS32 processor. −O1 Optimize for performance. −Os Optimize for space. −EL Produce little endian data output. −EB Produce little endian data output. −mpic Generate PIC. −mno−fp−as−gp−relax Suppress fp-as-gp relaxation for this file. −mb2bb−relax Back-to-back branch optimization. −mno−all−relax Suppress all relaxation for this file. −march=<arch name> Assemble for architecture <arch name> which could be v3, v3j, v3m, v3f, v3s, v2, v2j, v2f, v2s. −mbaseline=<baseline> Assemble for baseline <baseline> which could be v2, v3, v3m. −mfpu−freg=FREG Specify a FPU configuration. 0 8 SP / 4 DP registers 1 16 SP / 8 DP registers 2 32 SP / 16 DP registers 3 32 SP / 32 DP registers −mabi=abi Specify a abi version <abi> could be v1, v2, v2fp, v2fpp. −m[no−]mac Enable/Disable Multiply instructions support. −m[no−]div Enable/Disable Divide instructions support. −m[no−]16bit−ext Enable/Disable 16−bit extension −m[no−]dx−regs Enable/Disable d0/d1 registers −m[no−]perf−ext Enable/Disable Performance extension −m[no−]perf2−ext Enable/Disable Performance extension 2 −m[no−]string−ext Enable/Disable String extension −m[no−]reduced−regs Enable/Disable Reduced Register configuration (GPR16) option −m[no−]audio−isa−ext Enable/Disable AUDIO ISA extension −m[no−]fpu−sp−ext Enable/Disable FPU SP extension −m[no−]fpu−dp−ext Enable/Disable FPU DP extension −m[no−]fpu−fma Enable/Disable FPU fused-multiply-add instructions −mall−ext Turn on all extensions and instructions support The following options are available when as is configured for a PowerPC processor. −a32 Generate ELF32 or XCOFF32. −a64 Generate ELF64 or XCOFF64. −K PIC Set EF_PPC_RELOCATABLE_LIB in ELF flags. −mpwrx | −mpwr2 Generate code for POWER/2 (RIOS2). −mpwr Generate code for POWER (RIOS1) −m601 Generate code for PowerPC 601. −mppc, −mppc32, −m603, −m604 Generate code for PowerPC 603/604. −m403, −m405 Generate code for PowerPC 403/405. −m440 Generate code for PowerPC 440. BookE and some 405 instructions. −m464 Generate code for PowerPC 464. −m476 Generate code for PowerPC 476. −m7400, −m7410, −m7450, −m7455 Generate code for PowerPC 7400/7410/7450/7455. −m750cl, −mgekko, −mbroadway Generate code for PowerPC 750CL/Gekko/Broadway. −m821, −m850, −m860 Generate code for PowerPC 821/850/860. −mppc64, −m620 Generate code for PowerPC 620/625/630. −me500, −me500x2 Generate code for Motorola e500 core complex. −me500mc Generate code for Freescale e500mc core complex. −me500mc64 Generate code for Freescale e500mc64 core complex. −me5500 Generate code for Freescale e5500 core complex. −me6500 Generate code for Freescale e6500 core complex. −mspe Generate code for Motorola SPE instructions. −mspe2 Generate code for Freescale SPE2 instructions. −mtitan Generate code for AppliedMicro Titan core complex. −mppc64bridge Generate code for PowerPC 64, including bridge insns. −mbooke Generate code for 32−bit BookE. −ma2 Generate code for A2 architecture. −me300 Generate code for PowerPC e300 family. −maltivec Generate code for processors with AltiVec instructions. −mvle Generate code for Freescale PowerPC VLE instructions. −mvsx Generate code for processors with Vector-Scalar (VSX) instructions. −mhtm Generate code for processors with Hardware Transactional Memory instructions. −mpower4, −mpwr4 Generate code for Power4 architecture. −mpower5, −mpwr5, −mpwr5x Generate code for Power5 architecture. −mpower6, −mpwr6 Generate code for Power6 architecture. −mpower7, −mpwr7 Generate code for Power7 architecture. −mpower8, −mpwr8 Generate code for Power8 architecture. −mpower9, −mpwr9 Generate code for Power9 architecture. −mpower10, −mpwr10 Generate code for Power10 architecture. −mcell −mcell Generate code for Cell Broadband Engine architecture. −mcom Generate code Power/PowerPC common instructions. −many Generate code for any architecture (PWR/PWRX/PPC). −mregnames Allow symbolic names for registers. −mno−regnames Do not allow symbolic names for registers. −mrelocatable Support for GCC's −mrelocatable option. −mrelocatable−lib Support for GCC's −mrelocatable−lib option. −memb Set PPC_EMB bit in ELF flags. −mlittle, −mlittle−endian, −le Generate code for a little endian machine. −mbig, −mbig−endian, −be Generate code for a big endian machine. −msolaris Generate code for Solaris. −mno−solaris Do not generate code for Solaris. −nops=count If an alignment directive inserts more than count nops, put a branch at the beginning to skip execution of the nops. The following options are available when as is configured for a RISC-V processor. −fpic −fPIC Generate position-independent code −fno−pic Don't generate position-independent code (default) −march=ISA Select the base isa, as specified by ISA. For example −march=rv32ima. If this option and the architecture attributes aren't set, then assembler will check the default configure setting −−with−arch=ISA. −misa−spec=ISAspec Select the default isa spec version. If the version of ISA isn't set by −march, then assembler helps to set the version according to the default chosen spec. If this option isn't set, then assembler will check the default configure setting −−with−isa−spec=ISAspec. −mpriv−spec=PRIVspec Select the privileged spec version. We can decide whether the CSR is valid or not according to the chosen spec. If this option and the privilege attributes aren't set, then assembler will check the default configure setting −−with−priv−spec=PRIVspec. −mabi=ABI Selects the ABI, which is either "ilp32" or "lp64", optionally followed by "f", "d", or "q" to indicate single-precision, double-precision, or quad-precision floating-point calling convention, or none to indicate the soft-float calling convention. Also, "ilp32" can optionally be followed by "e" to indicate the RVE ABI, which is always soft-float. −mrelax Take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. (default) −mno−relax Don't do linker relaxations. −march−attr Generate the default contents for the riscv elf attribute section if the .attribute directives are not set. This section is used to record the information that a linker or runtime loader needs to check compatibility. This information includes ISA string, stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of privileged specification. −mno−arch−attr Don't generate the default riscv elf attribute section if the .attribute directives are not set. −mcsr−check Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. The ISA-dependent CSR are only valid when the specific ISA is set. The read-only CSR can not be written by the CSR instructions. −mno−csr−check Don't do CSR checking. −mlittle−endian Generate code for a little endian machine. −mbig−endian Generate code for a big endian machine. See the info pages for documentation of the RX-specific options. The following options are available when as is configured for the s390 processor family. −m31 −m64 Select the word size, either 31/32 bits or 64 bits. −mesa −mzarch Select the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch). −march=processor Specify which s390 processor variant is the target, g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9−109, z9−ec (or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11), z14 (or arch12), z15 (or arch13), or z16 (or arch14). −mregnames −mno−regnames Allow or disallow symbolic names for registers. −mwarn−areg−zero Warn whenever the operand for a base or index register has been specified but evaluates to zero. The following options are available when as is configured for a TMS320C6000 processor. −march=arch Enable (only) instructions from architecture arch. By default, all instructions are permitted. The following values of arch are accepted: \*(C`c62x\*(C'\fR, \*(C`c64x\*(C'\fR, \f(CW\*(C`c64x+\*(C'\fR, \f(CW\*(C`c67x\*(C'\fR, \f(CW\*(C`c67x+\*(C'\fR, \f(CW\*(C`c674x\*(C'\fR. −mdsbt −mno−dsbt The −mdsbt option causes the assembler to generate the \*(C`Tag_ABI_DSBT\*(C'\fR attribute with a value of 1, indicating that the code is using DSBT addressing. The −mno−dsbt option, the default, causes the tag to have a value of 0, indicating that the code does not use DSBT addressing. The linker will emit a warning if objects of different type (DSBT and non-DSBT) are linked together. −mpid=no −mpid=near −mpid=far The −mpid= option causes the assembler to generate the \*(C`Tag_ABI_PID\*(C'\fR attribute with a value indicating the form of data addressing used by the code. −mpid=no, the default, indicates position-dependent data addressing, −mpid=near indicates position-independent addressing with GOT accesses using near DP addressing, and −mpid=far indicates position-independent addressing with GOT accesses using far DP addressing. The linker will emit a warning if objects built with different settings of this option are linked together. −mpic −mno−pic The −mpic option causes the assembler to generate the \*(C`Tag_ABI_PIC\*(C'\fR attribute with a value of 1, indicating that the code is using position-independent code addressing, The \*(C`\-mno\-pic\*(C'\fR option, the default, causes the tag to have a value of 0, indicating position-dependent code addressing. The linker will emit a warning if objects of different type (position-dependent and position-independent) are linked together. −mbig−endian −mlittle−endian Generate code for the specified endianness. The default is little-endian. The following options are available when as is configured for a TILE-Gx processor. −m32 | −m64 Select the word size, either 32 bits or 64 bits. −EB | −EL Select the endianness, either big-endian (−EB) or little-endian (−EL). The following option is available when as is configured for a Visium processor. −mtune=arch This option specifies the target architecture. If an attempt is made to assemble an instruction that will not execute on the target architecture, the assembler will issue an error message. The following names are recognized: \*(C`mcm24\*(C'\fR \*(C`mcm\*(C'\fR \*(C`gr5\*(C'\fR \*(C`gr6\*(C'\fR The following options are available when as is configured for an Xtensa processor. −−text−section−literals | −−no−text−section−literals Control the treatment of literal pools. The default is −−no−text−section−literals, which places literals in separate sections in the output file. This allows the literal pool to be placed in a data RAM/ROM. With −−text−section−literals, the literals are interspersed in the text section in order to keep them as close as possible to their references. This may be necessary for large assembly files, where the literals would otherwise be out of range of the \*(C`L32R\*(C'\fR instructions in the text section. Literals are grouped into pools following \*(C`.literal_position\*(C'\fR directives or preceding \*(C`ENTRY\*(C'\fR instructions. These options only affect literals referenced via PC-relative \*(C`L32R\*(C'\fR instructions; literals for absolute mode \*(C`L32R\*(C'\fR instructions are handled separately. −−auto−litpools | −−no−auto−litpools Control the treatment of literal pools. The default is −−no−auto−litpools, which in the absence of −−text−section−literals places literals in separate sections in the output file. This allows the literal pool to be placed in a data RAM/ROM. With −−auto−litpools, the literals are interspersed in the text section in order to keep them as close as possible to their references, explicit \*(C`.literal_position\*(C'\fR directives are not required. This may be necessary for very large functions, where single literal pool at the beginning of the function may not be reachable by \*(C`L32R\*(C'\fR instructions at the end. These options only affect literals referenced via PC-relative \*(C`L32R\*(C'\fR instructions; literals for absolute mode \*(C`L32R\*(C'\fR instructions are handled separately. When used together with −−text−section−literals, −−auto−litpools takes precedence. −−absolute−literals | −−no−absolute−literals Indicate to the assembler whether \*(C`L32R\*(C'\fR instructions use absolute or PC-relative addressing. If the processor includes the absolute addressing option, the default is to use absolute \*(C`L32R\*(C'\fR relocations. Otherwise, only the PC-relative \*(C`L32R\*(C'\fR relocations can be used. −−target−align | −−no−target−align Enable or disable automatic alignment to reduce branch penalties at some expense in code size. This optimization is enabled by default. Note that the assembler will always align instructions like \*(C`LOOP\*(C'\fR that have fixed alignment requirements. −−longcalls | −−no−longcalls Enable or disable transformation of call instructions to allow calls across a greater range of addresses. This option should be used when call targets can potentially be out of range. It may degrade both code size and performance, but the linker can generally optimize away the unnecessary overhead when a call ends up within range. The default is −−no−longcalls. −−transform | −−no−transform Enable or disable all assembler transformations of Xtensa instructions, including both relaxation and optimization. The default is −−transform; −−no−transform should only be used in the rare cases when the instructions must be exactly as specified in the assembly source. Using −−no−transform causes out of range instruction operands to be errors. −−rename−section oldname=newname Rename the oldname section to newname. This option can be used multiple times to rename multiple sections. −−trampolines | −−no−trampolines Enable or disable transformation of jump instructions to allow jumps across a greater range of addresses. This option should be used when jump targets can potentially be out of range. In the absence of such jumps this option does not affect code size or performance. The default is −−trampolines. −−abi−windowed | −−abi−call0 Choose ABI tag written to the \*(C`.xtensa.info\*(C'\fR section. ABI tag indicates ABI of the assembly code. A warning is issued by the linker on an attempt to link object files with inconsistent ABI tags. Default ABI is chosen by the Xtensa core configuration. The following options are available when as is configured for an Z80 processor. @chapter Z80 Dependent Features
Command-line Options−march=CPU[−EXT...][+EXT...] This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: \*(C`z80\*(C'\fR, \*(C`z180\*(C'\fR, \*(C`ez80\*(C'\fR, \*(C`gbz80\*(C'\fR, \*(C`z80n\*(C'\fR, \*(C`r800\*(C'\fR. In addition to the basic instruction set, the assembler can be told to accept some extention mnemonics. For example, \*(C`\-march=z180+sli+infc\*(C'\fR extends \fIz180\fR with \fISLI\fR instructions and IN F,(C). The following extentions are currently supported: \*(C`full\*(C'\fR (all known instructions), \*(C`adl\*(C'\fR (ADL CPU mode by default, eZ80 only), \*(C`sli\*(C'\fR (instruction known as \fISLI\fR, \fISLL\fR or \fISL1\fR), \*(C`xyhl\*(C'\fR (instructions with halves of index registers: \fIIXL\fR, \fIIXH\fR, IYL, IYH), \*(C`xdcb\*(C'\fR (instructions like \fIRotOp (II+d),R\fR and \fIBitOp n,(II+d),R\fR), \*(C`infc\*(C'\fR (instruction \fIIN F,(C)\fR or \fIIN (C)\fR), \*(C`outc0\*(C'\fR (instruction \fIOUT (C),0\fR). Note that rather than extending a basic instruction set, the extention mnemonics starting with \*(C`\-\*(C'\fR revoke the respective functionality: \*(C`\-march=z80\-full+xyhl\*(C'\fR first removes all default extentions and adds support for index registers halves only. If this option is not specified then \*(C`\-march=z80+xyhl+infc\*(C'\fR is assumed. −local−prefix=prefix Mark all labels with specified prefix as local. But such label can be marked global explicitly in the code. This option do not change default local label prefix \*(C`.L\*(C'\fR, it is just adds new one. −colonless Accept colonless labels. All symbols at line begin are treated as labels. −sdcc Accept assembler code produced by SDCC. −fp−s=FORMAT Single precision floating point numbers format. Default: ieee754 (32 bit). −fp−d=FORMAT Double precision floating point numbers format. Default: ieee754 (64 bit).
SEE ALSOgcc (1), ld (1), and the Info entries for binutils and ld.
COPYRIGHTCopyright (c) 1991−2022 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License". 0
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) (rof_escape_sequence|91|as.1|388|\*(C`gcc\*(C'\fR for use by the linker |GNU C compiler \f(CW\*(C`gcc\*(C'\fR for use by the linker
) (rof_escape_sequence|91|as.1|389|\*(C`ld\*(C'\fR. Nevertheless, we've tried to make \fBas\fR |\&\f(CW\*(C`ld\*(C'\fR. Nevertheless, we've tried to make \fBas\fR
) (rof_escape_sequence|91|as.1|542|\*(C`.set\*(C'\fR pseudo-op. |use of a \f(CW\*(C`.set\*(C'\fR pseudo-op.
) (rof_escape_sequence|91|as.1|555|\*(C`.debug_info\*(C'\fR and |ECOFF or DWARF2. When the debug format is DWARF then a \f(CW\*(C`.debug_info\*(C'\fR and
) (rof_escape_sequence|91|as.1|556|\*(C`.debug_line\*(C'\fR section is only emitted when the assembly file doesn't |\&\f(CW\*(C`.debug_line\*(C'\fR section is only emitted when the assembly file doesn't
) (rof_escape_sequence|91|as.1|623|\*(C`STT_COMMON\*(C'\fR type. The default can be controlled |symbols with the \f(CW\*(C`STT_COMMON\*(C'\fR type. The default can be controlled
) (rof_escape_sequence|91|as.1|643|\*(C`.include\*(C'\fR directives. |Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives.
) (rof_escape_sequence|91|as.1|761|\*(C`ilp32\*(C'\fR and \f(CW\*(C`lp64\*(C'\fR, which decides the generated object |are: \f(CW\*(C`ilp32\*(C'\fR and \f(CW\*(C`lp64\*(C'\fR, which decides the generated object
) (rof_escape_sequence|91|as.1|762|\*(C`lp64\*(C'\fR. |file in ELF32 and ELF64 format respectively. The default is \f(CW\*(C`lp64\*(C'\fR.
) (rof_escape_sequence|91|as.1|768|\*(C`cortex\-a34\*(C'\fR, |\&\f(CW\*(C`cortex\-a34\*(C'\fR,
) (rof_escape_sequence|91|as.1|769|\*(C`cortex\-a35\*(C'\fR, |\&\f(CW\*(C`cortex\-a35\*(C'\fR,
) (rof_escape_sequence|91|as.1|770|\*(C`cortex\-a53\*(C'\fR, |\&\f(CW\*(C`cortex\-a53\*(C'\fR,
) (rof_escape_sequence|91|as.1|771|\*(C`cortex\-a55\*(C'\fR, |\&\f(CW\*(C`cortex\-a55\*(C'\fR,
) (rof_escape_sequence|91|as.1|772|\*(C`cortex\-a57\*(C'\fR, |\&\f(CW\*(C`cortex\-a57\*(C'\fR,
) (rof_escape_sequence|91|as.1|773|\*(C`cortex\-a65\*(C'\fR, |\&\f(CW\*(C`cortex\-a65\*(C'\fR,
) (rof_escape_sequence|91|as.1|774|\*(C`cortex\-a65ae\*(C'\fR, |\&\f(CW\*(C`cortex\-a65ae\*(C'\fR,
) (rof_escape_sequence|91|as.1|775|\*(C`cortex\-a72\*(C'\fR, |\&\f(CW\*(C`cortex\-a72\*(C'\fR,
) (rof_escape_sequence|91|as.1|776|\*(C`cortex\-a73\*(C'\fR, |\&\f(CW\*(C`cortex\-a73\*(C'\fR,
) (rof_escape_sequence|91|as.1|777|\*(C`cortex\-a75\*(C'\fR, |\&\f(CW\*(C`cortex\-a75\*(C'\fR,
) (rof_escape_sequence|91|as.1|778|\*(C`cortex\-a76\*(C'\fR, |\&\f(CW\*(C`cortex\-a76\*(C'\fR,
) (rof_escape_sequence|91|as.1|779|\*(C`cortex\-a76ae\*(C'\fR, |\&\f(CW\*(C`cortex\-a76ae\*(C'\fR,
) (rof_escape_sequence|91|as.1|780|\*(C`cortex\-a77\*(C'\fR, |\&\f(CW\*(C`cortex\-a77\*(C'\fR,
) (rof_escape_sequence|91|as.1|781|\*(C`cortex\-a78\*(C'\fR, |\&\f(CW\*(C`cortex\-a78\*(C'\fR,
) (rof_escape_sequence|91|as.1|782|\*(C`cortex\-a78ae\*(C'\fR, |\&\f(CW\*(C`cortex\-a78ae\*(C'\fR,
) (rof_escape_sequence|91|as.1|783|\*(C`cortex\-a78c\*(C'\fR, |\&\f(CW\*(C`cortex\-a78c\*(C'\fR,
) (rof_escape_sequence|91|as.1|784|\*(C`cortex\-a510\*(C'\fR, |\&\f(CW\*(C`cortex\-a510\*(C'\fR,
) (rof_escape_sequence|91|as.1|785|\*(C`cortex\-a710\*(C'\fR, |\&\f(CW\*(C`cortex\-a710\*(C'\fR,
) (rof_escape_sequence|91|as.1|786|\*(C`ares\*(C'\fR, |\&\f(CW\*(C`ares\*(C'\fR,
) (rof_escape_sequence|91|as.1|787|\*(C`exynos\-m1\*(C'\fR, |\&\f(CW\*(C`exynos\-m1\*(C'\fR,
) (rof_escape_sequence|91|as.1|788|\*(C`falkor\*(C'\fR, |\&\f(CW\*(C`falkor\*(C'\fR,
) (rof_escape_sequence|91|as.1|789|\*(C`neoverse\-n1\*(C'\fR, |\&\f(CW\*(C`neoverse\-n1\*(C'\fR,
) (rof_escape_sequence|91|as.1|790|\*(C`neoverse\-n2\*(C'\fR, |\&\f(CW\*(C`neoverse\-n2\*(C'\fR,
) (rof_escape_sequence|91|as.1|791|\*(C`neoverse\-e1\*(C'\fR, |\&\f(CW\*(C`neoverse\-e1\*(C'\fR,
) (rof_escape_sequence|91|as.1|792|\*(C`neoverse\-v1\*(C'\fR, |\&\f(CW\*(C`neoverse\-v1\*(C'\fR,
) (rof_escape_sequence|91|as.1|793|\*(C`qdf24xx\*(C'\fR, |\&\f(CW\*(C`qdf24xx\*(C'\fR,
) (rof_escape_sequence|91|as.1|794|\*(C`saphira\*(C'\fR, |\&\f(CW\*(C`saphira\*(C'\fR,
) (rof_escape_sequence|91|as.1|795|\*(C`thunderx\*(C'\fR, |\&\f(CW\*(C`thunderx\*(C'\fR,
) (rof_escape_sequence|91|as.1|796|\*(C`vulcan\*(C'\fR, |\&\f(CW\*(C`vulcan\*(C'\fR,
) (rof_escape_sequence|91|as.1|797|\*(C`xgene1\*(C'\fR |\&\f(CW\*(C`xgene1\*(C'\fR
) (rof_escape_sequence|91|as.1|798|\*(C`xgene2\*(C'\fR, |\&\f(CW\*(C`xgene2\*(C'\fR,
) (rof_escape_sequence|91|as.1|799|\*(C`cortex\-r82\*(C'\fR, |\&\f(CW\*(C`cortex\-r82\*(C'\fR,
) (rof_escape_sequence|91|as.1|800|\*(C`cortex\-x1\*(C'\fR, |\&\f(CW\*(C`cortex\-x1\*(C'\fR,
) (rof_escape_sequence|91|as.1|802|\*(C`cortex\-x2\*(C'\fR. |\&\f(CW\*(C`cortex\-x2\*(C'\fR.
) (rof_escape_sequence|91|as.1|803|\*(C`all\*(C'\fR may be used to allow the assembler to accept |The special name \f(CW\*(C`all\*(C'\fR may be used to allow the assembler to accept
) (rof_escape_sequence|91|as.1|820|\*(C`armv8\-a\*(C'\fR, |following architecture names are recognized: \f(CW\*(C`armv8\-a\*(C'\fR,
) (rof_escape_sequence|91|as.1|821|\*(C`armv8.1\-a\*(C'\fR, \f(CW\*(C`armv8.2\-a\*(C'\fR, \f(CW\*(C`armv8.3\-a\*(C'\fR, \f(CW\*(C`armv8.4\-a\*(C'\fR |\&\f(CW\*(C`armv8.1\-a\*(C'\fR, \f(CW\*(C`armv8.2\-a\*(C'\fR, \f(CW\*(C`armv8.3\-a\*(C'\fR, \f(CW\*(C`armv8.4\-a\*(C'\fR
) (rof_escape_sequence|91|as.1|822|\*(C`armv8.5\-a\*(C'\fR, \f(CW\*(C`armv8.6\-a\*(C'\fR, \f(CW\*(C`armv8.7\-a\*(C'\fR, \f(CW\*(C`armv8.8\-a\*(C'\fR, |\&\f(CW\*(C`armv8.5\-a\*(C'\fR, \f(CW\*(C`armv8.6\-a\*(C'\fR, \f(CW\*(C`armv8.7\-a\*(C'\fR, \f(CW\*(C`armv8.8\-a\*(C'\fR,
) (rof_escape_sequence|91|as.1|823|\*(C`armv8\-r\*(C'\fR, \f(CW\*(C`armv9\-a\*(C'\fR, \f(CW\*(C`armv9.1\-a\*(C'\fR, \f(CW\*(C`armv9.2\-a\*(C'\fR, |\&\f(CW\*(C`armv8\-r\*(C'\fR, \f(CW\*(C`armv9\-a\*(C'\fR, \f(CW\*(C`armv9.1\-a\*(C'\fR, \f(CW\*(C`armv9.2\-a\*(C'\fR,
) (rof_escape_sequence|91|as.1|824|\*(C`armv9.3\-a\*(C'\fR. |and \f(CW\*(C`armv9.3\-a\*(C'\fR.
) (rof_escape_sequence|91|as.1|848|\*(C`.arch\*(C'\fR directive. |error message. This option is equivalent to the \f(CW\*(C`.arch\*(C'\fR directive.
) (rof_escape_sequence|91|as.1|852|\*(C`21064a\*(C'\fR, |\&\f(CW\*(C`21064a\*(C'\fR,
) (rof_escape_sequence|91|as.1|856|\*(C`21164a\*(C'\fR, |\&\f(CW\*(C`21164a\*(C'\fR,
) (rof_escape_sequence|91|as.1|857|\*(C`21164pc\*(C'\fR, |\&\f(CW\*(C`21164pc\*(C'\fR,
) (rof_escape_sequence|91|as.1|859|\*(C`21264a\*(C'\fR, |\&\f(CW\*(C`21264a\*(C'\fR,
) (rof_escape_sequence|91|as.1|860|\*(C`21264b\*(C'\fR, |\&\f(CW\*(C`21264b\*(C'\fR,
) (rof_escape_sequence|91|as.1|861|\*(C`ev4\*(C'\fR, |\&\f(CW\*(C`ev4\*(C'\fR,
) (rof_escape_sequence|91|as.1|862|\*(C`ev5\*(C'\fR, |\&\f(CW\*(C`ev5\*(C'\fR,
) (rof_escape_sequence|91|as.1|863|\*(C`lca45\*(C'\fR, |\&\f(CW\*(C`lca45\*(C'\fR,
) (rof_escape_sequence|91|as.1|864|\*(C`ev5\*(C'\fR, |\&\f(CW\*(C`ev5\*(C'\fR,
) (rof_escape_sequence|91|as.1|865|\*(C`ev56\*(C'\fR, |\&\f(CW\*(C`ev56\*(C'\fR,
) (rof_escape_sequence|91|as.1|866|\*(C`pca56\*(C'\fR, |\&\f(CW\*(C`pca56\*(C'\fR,
) (rof_escape_sequence|91|as.1|867|\*(C`ev6\*(C'\fR, |\&\f(CW\*(C`ev6\*(C'\fR,
) (rof_escape_sequence|91|as.1|868|\*(C`ev67\*(C'\fR, |\&\f(CW\*(C`ev67\*(C'\fR,
) (rof_escape_sequence|91|as.1|869|\*(C`ev68\*(C'\fR. |\&\f(CW\*(C`ev68\*(C'\fR.
) (rof_escape_sequence|91|as.1|870|\*(C`all\*(C'\fR may be used to allow the assembler to accept |The special name \f(CW\*(C`all\*(C'\fR may be used to allow the assembler to accept
) (rof_escape_sequence|91|as.1|873|\*(C`.arch\*(C'\fR, |In order to support existing practice in OSF/1 with respect to \f(CW\*(C`.arch\*(C'\fR,
) (rof_escape_sequence|91|as.1|876|\*(C`ev4\*(C'\fR) do not. |instructions, while the "electro-vlasic" names (e.g. \f(CW\*(C`ev4\*(C'\fR) do not.
) (rof_escape_sequence|91|as.1|883|\*(C`.mdebug\*(C'\fR encapsulation for |Enables or disables the generation of \f(CW\*(C`.mdebug\*(C'\fR encapsulation for
) (rof_escape_sequence|91|as.1|885|\*(C`.mdebug\*(C'\fR when the first stabs directive is seen. |enable \f(CW\*(C`.mdebug\*(C'\fR when the first stabs directive is seen.
) (rof_escape_sequence|91|as.1|901|\*(C`\-replace\*(C'\fR is the default. See section 1.4.1 of the OpenVMS Linker |\&\f(CW\*(C`\-replace\*(C'\fR is the default. See section 1.4.1 of the OpenVMS Linker
) (rof_escape_sequence|91|as.1|911|\*(C`.bss\*(C'\fR, |A local common symbol larger than \fIsize\fR is placed in \f(CW\*(C`.bss\*(C'\fR,
) (rof_escape_sequence|91|as.1|912|\*(C`.sbss\*(C'\fR. |while smaller symbols are placed in \f(CW\*(C`.sbss\*(C'\fR.
) (rof_escape_sequence|91|as.1|973|\*(C`\-mcpu=\*(C'\fR option. The assembler will issue an |\&\f(CW\*(C`\-mcpu=\*(C'\fR option. The assembler will issue an
) (rof_escape_sequence|91|as.1|977|\*(C`bf504\*(C'\fR, |\&\f(CW\*(C`bf504\*(C'\fR,
) (rof_escape_sequence|91|as.1|978|\*(C`bf506\*(C'\fR, |\&\f(CW\*(C`bf506\*(C'\fR,
) (rof_escape_sequence|91|as.1|979|\*(C`bf512\*(C'\fR, |\&\f(CW\*(C`bf512\*(C'\fR,
) (rof_escape_sequence|91|as.1|980|\*(C`bf514\*(C'\fR, |\&\f(CW\*(C`bf514\*(C'\fR,
) (rof_escape_sequence|91|as.1|981|\*(C`bf516\*(C'\fR, |\&\f(CW\*(C`bf516\*(C'\fR,
) (rof_escape_sequence|91|as.1|982|\*(C`bf518\*(C'\fR, |\&\f(CW\*(C`bf518\*(C'\fR,
) (rof_escape_sequence|91|as.1|983|\*(C`bf522\*(C'\fR, |\&\f(CW\*(C`bf522\*(C'\fR,
) (rof_escape_sequence|91|as.1|984|\*(C`bf523\*(C'\fR, |\&\f(CW\*(C`bf523\*(C'\fR,
) (rof_escape_sequence|91|as.1|985|\*(C`bf524\*(C'\fR, |\&\f(CW\*(C`bf524\*(C'\fR,
) (rof_escape_sequence|91|as.1|986|\*(C`bf525\*(C'\fR, |\&\f(CW\*(C`bf525\*(C'\fR,
) (rof_escape_sequence|91|as.1|987|\*(C`bf526\*(C'\fR, |\&\f(CW\*(C`bf526\*(C'\fR,
) (rof_escape_sequence|91|as.1|988|\*(C`bf527\*(C'\fR, |\&\f(CW\*(C`bf527\*(C'\fR,
) (rof_escape_sequence|91|as.1|989|\*(C`bf531\*(C'\fR, |\&\f(CW\*(C`bf531\*(C'\fR,
) (rof_escape_sequence|91|as.1|990|\*(C`bf532\*(C'\fR, |\&\f(CW\*(C`bf532\*(C'\fR,
) (rof_escape_sequence|91|as.1|991|\*(C`bf533\*(C'\fR, |\&\f(CW\*(C`bf533\*(C'\fR,
) (rof_escape_sequence|91|as.1|992|\*(C`bf534\*(C'\fR, |\&\f(CW\*(C`bf534\*(C'\fR,
) (rof_escape_sequence|91|as.1|993|\*(C`bf535\*(C'\fR (not implemented yet), |\&\f(CW\*(C`bf535\*(C'\fR (not implemented yet),
) (rof_escape_sequence|91|as.1|994|\*(C`bf536\*(C'\fR, |\&\f(CW\*(C`bf536\*(C'\fR,
) (rof_escape_sequence|91|as.1|995|\*(C`bf537\*(C'\fR, |\&\f(CW\*(C`bf537\*(C'\fR,
) (rof_escape_sequence|91|as.1|996|\*(C`bf538\*(C'\fR, |\&\f(CW\*(C`bf538\*(C'\fR,
) (rof_escape_sequence|91|as.1|997|\*(C`bf539\*(C'\fR, |\&\f(CW\*(C`bf539\*(C'\fR,
) (rof_escape_sequence|91|as.1|998|\*(C`bf542\*(C'\fR, |\&\f(CW\*(C`bf542\*(C'\fR,
) (rof_escape_sequence|91|as.1|999|\*(C`bf542m\*(C'\fR, |\&\f(CW\*(C`bf542m\*(C'\fR,
) (rof_escape_sequence|91|as.1|1000|\*(C`bf544\*(C'\fR, |\&\f(CW\*(C`bf544\*(C'\fR,
) (rof_escape_sequence|91|as.1|1001|\*(C`bf544m\*(C'\fR, |\&\f(CW\*(C`bf544m\*(C'\fR,
) (rof_escape_sequence|91|as.1|1002|\*(C`bf547\*(C'\fR, |\&\f(CW\*(C`bf547\*(C'\fR,
) (rof_escape_sequence|91|as.1|1003|\*(C`bf547m\*(C'\fR, |\&\f(CW\*(C`bf547m\*(C'\fR,
) (rof_escape_sequence|91|as.1|1004|\*(C`bf548\*(C'\fR, |\&\f(CW\*(C`bf548\*(C'\fR,
) (rof_escape_sequence|91|as.1|1005|\*(C`bf548m\*(C'\fR, |\&\f(CW\*(C`bf548m\*(C'\fR,
) (rof_escape_sequence|91|as.1|1006|\*(C`bf549\*(C'\fR, |\&\f(CW\*(C`bf549\*(C'\fR,
) (rof_escape_sequence|91|as.1|1007|\*(C`bf549m\*(C'\fR, |\&\f(CW\*(C`bf549m\*(C'\fR,
) (rof_escape_sequence|91|as.1|1008|\*(C`bf561\*(C'\fR, |\&\f(CW\*(C`bf561\*(C'\fR,
) (rof_escape_sequence|91|as.1|1010|\*(C`bf592\*(C'\fR. |\&\f(CW\*(C`bf592\*(C'\fR.
) (rof_escape_sequence|91|as.1|1078|\*(C`jbf\*(C'\fR, \f(CW\*(C`jbt\*(C'\fR, and \f(CW\*(C`jbr\*(C'\fR to \f(CW\*(C`jmpi\*(C'\fR. |\&\f(CW\*(C`jbf\*(C'\fR, \f(CW\*(C`jbt\*(C'\fR, and \f(CW\*(C`jbr\*(C'\fR to \f(CW\*(C`jmpi\*(C'\fR.
) (rof_escape_sequence|91|as.1|1080|\*(C`jmpi\*(C'\fR |It is ignored on CK801 and CK802 targets, which do not support the \f(CW\*(C`jmpi\*(C'\fR
) (rof_escape_sequence|91|as.1|1088|\*(C`R_CKCORE_PCREL_IMM26BY2\*(C'\fR relocations for \f(CW\*(C`bsr\*(C'\fR |Pass through \f(CW\*(C`R_CKCORE_PCREL_IMM26BY2\*(C'\fR relocations for \f(CW\*(C`bsr\*(C'\fR
) (rof_escape_sequence|91|as.1|1104|\*(C`jbsr\*(C'\fR instructions to \f(CW\*(C`bsr\*(C'\fR. |Enable/disable transformation of \f(CW\*(C`jbsr\*(C'\fR instructions to \f(CW\*(C`bsr\*(C'\fR.
) (rof_escape_sequence|91|as.1|1118|\*(C`jsri\*(C'\fR instructions to \f(CW\*(C`bsr\*(C'\fR. |Enable/disable transformation of \f(CW\*(C`jsri\*(C'\fR instructions to \f(CW\*(C`bsr\*(C'\fR.
) (rof_escape_sequence|91|as.1|1126|\*(C`lrw\*(C'\fR instructions into a |Enable/disable transformation of \f(CW\*(C`lrw\*(C'\fR instructions into a
) (rof_escape_sequence|91|as.1|1127|\*(C`movih\*(C'\fR/\f(CW\*(C`ori\*(C'\fR pair. |\&\f(CW\*(C`movih\*(C'\fR/\f(CW\*(C`ori\*(C'\fR pair.
) (rof_escape_sequence|91|as.1|1134|\*(C`lrw\*(C'\fR instructions. |Enable/disable extended \f(CW\*(C`lrw\*(C'\fR instructions.
) (rof_escape_sequence|91|as.1|1169|\*(C`\-mcpu=\*(C'\fR to specify |These features are also enabled implicitly by using \f(CW\*(C`\-mcpu=\*(C'\fR to specify
) (rof_escape_sequence|91|as.1|1214|\*(C`as\*(C'\fR has one |The Renesas H8/300 version of \f(CW\*(C`as\*(C'\fR has one
) (rof_escape_sequence|91|as.1|1223|\*(C`h8300h\*(C'\fR, |\&\f(CW\*(C`h8300h\*(C'\fR,
) (rof_escape_sequence|91|as.1|1224|\*(C`h8300hn\*(C'\fR, |\&\f(CW\*(C`h8300hn\*(C'\fR,
) (rof_escape_sequence|91|as.1|1225|\*(C`h8300s\*(C'\fR, |\&\f(CW\*(C`h8300s\*(C'\fR,
) (rof_escape_sequence|91|as.1|1226|\*(C`h8300sn\*(C'\fR, |\&\f(CW\*(C`h8300sn\*(C'\fR,
) (rof_escape_sequence|91|as.1|1227|\*(C`h8300sx\*(C'\fR and |\&\f(CW\*(C`h8300sx\*(C'\fR and
) (rof_escape_sequence|91|as.1|1228|\*(C`h8300sxn\*(C'\fR. |\&\f(CW\*(C`h8300sxn\*(C'\fR.
) (rof_escape_sequence|91|as.1|1262|\*(C`i8086\*(C'\fR, |\&\f(CW\*(C`i8086\*(C'\fR,
) (rof_escape_sequence|91|as.1|1263|\*(C`i186\*(C'\fR, |\&\f(CW\*(C`i186\*(C'\fR,
) (rof_escape_sequence|91|as.1|1264|\*(C`i286\*(C'\fR, |\&\f(CW\*(C`i286\*(C'\fR,
) (rof_escape_sequence|91|as.1|1265|\*(C`i386\*(C'\fR, |\&\f(CW\*(C`i386\*(C'\fR,
) (rof_escape_sequence|91|as.1|1266|\*(C`i486\*(C'\fR, |\&\f(CW\*(C`i486\*(C'\fR,
) (rof_escape_sequence|91|as.1|1267|\*(C`i586\*(C'\fR, |\&\f(CW\*(C`i586\*(C'\fR,
) (rof_escape_sequence|91|as.1|1268|\*(C`i686\*(C'\fR, |\&\f(CW\*(C`i686\*(C'\fR,
) (rof_escape_sequence|91|as.1|1269|\*(C`pentium\*(C'\fR, |\&\f(CW\*(C`pentium\*(C'\fR,
) (rof_escape_sequence|91|as.1|1270|\*(C`pentiumpro\*(C'\fR, |\&\f(CW\*(C`pentiumpro\*(C'\fR,
) (rof_escape_sequence|91|as.1|1271|\*(C`pentiumii\*(C'\fR, |\&\f(CW\*(C`pentiumii\*(C'\fR,
) (rof_escape_sequence|91|as.1|1272|\*(C`pentiumiii\*(C'\fR, |\&\f(CW\*(C`pentiumiii\*(C'\fR,
) (rof_escape_sequence|91|as.1|1273|\*(C`pentium4\*(C'\fR, |\&\f(CW\*(C`pentium4\*(C'\fR,
) (rof_escape_sequence|91|as.1|1274|\*(C`prescott\*(C'\fR, |\&\f(CW\*(C`prescott\*(C'\fR,
) (rof_escape_sequence|91|as.1|1275|\*(C`nocona\*(C'\fR, |\&\f(CW\*(C`nocona\*(C'\fR,
) (rof_escape_sequence|91|as.1|1276|\*(C`core\*(C'\fR, |\&\f(CW\*(C`core\*(C'\fR,
) (rof_escape_sequence|91|as.1|1277|\*(C`core2\*(C'\fR, |\&\f(CW\*(C`core2\*(C'\fR,
) (rof_escape_sequence|91|as.1|1278|\*(C`corei7\*(C'\fR, |\&\f(CW\*(C`corei7\*(C'\fR,
) (rof_escape_sequence|91|as.1|1279|\*(C`iamcu\*(C'\fR, |\&\f(CW\*(C`iamcu\*(C'\fR,
) (rof_escape_sequence|91|as.1|1280|\*(C`k6\*(C'\fR, |\&\f(CW\*(C`k6\*(C'\fR,
) (rof_escape_sequence|91|as.1|1281|\*(C`k6_2\*(C'\fR, |\&\f(CW\*(C`k6_2\*(C'\fR,
) (rof_escape_sequence|91|as.1|1282|\*(C`athlon\*(C'\fR, |\&\f(CW\*(C`athlon\*(C'\fR,
) (rof_escape_sequence|91|as.1|1283|\*(C`opteron\*(C'\fR, |\&\f(CW\*(C`opteron\*(C'\fR,
) (rof_escape_sequence|91|as.1|1284|\*(C`k8\*(C'\fR, |\&\f(CW\*(C`k8\*(C'\fR,
) (rof_escape_sequence|91|as.1|1285|\*(C`amdfam10\*(C'\fR, |\&\f(CW\*(C`amdfam10\*(C'\fR,
) (rof_escape_sequence|91|as.1|1286|\*(C`bdver1\*(C'\fR, |\&\f(CW\*(C`bdver1\*(C'\fR,
) (rof_escape_sequence|91|as.1|1287|\*(C`bdver2\*(C'\fR, |\&\f(CW\*(C`bdver2\*(C'\fR,
) (rof_escape_sequence|91|as.1|1288|\*(C`bdver3\*(C'\fR, |\&\f(CW\*(C`bdver3\*(C'\fR,
) (rof_escape_sequence|91|as.1|1289|\*(C`bdver4\*(C'\fR, |\&\f(CW\*(C`bdver4\*(C'\fR,
) (rof_escape_sequence|91|as.1|1290|\*(C`znver1\*(C'\fR, |\&\f(CW\*(C`znver1\*(C'\fR,
) (rof_escape_sequence|91|as.1|1291|\*(C`znver2\*(C'\fR, |\&\f(CW\*(C`znver2\*(C'\fR,
) (rof_escape_sequence|91|as.1|1292|\*(C`znver3\*(C'\fR, |\&\f(CW\*(C`znver3\*(C'\fR,
) (rof_escape_sequence|91|as.1|1293|\*(C`btver1\*(C'\fR, |\&\f(CW\*(C`btver1\*(C'\fR,
) (rof_escape_sequence|91|as.1|1294|\*(C`btver2\*(C'\fR, |\&\f(CW\*(C`btver2\*(C'\fR,
) (rof_escape_sequence|91|as.1|1295|\*(C`generic32\*(C'\fR and |\&\f(CW\*(C`generic32\*(C'\fR and
) (rof_escape_sequence|91|as.1|1296|\*(C`generic64\*(C'\fR. |\&\f(CW\*(C`generic64\*(C'\fR.
) (rof_escape_sequence|91|as.1|1300|\*(C`\-march=i686+sse4+vmx\*(C'\fR extends \fIi686\fR with \fIsse4\fR and |\&\f(CW\*(C`\-march=i686+sse4+vmx\*(C'\fR extends \fIi686\fR with \fIsse4\fR and
) (rof_escape_sequence|91|as.1|1306|\*(C`no87\*(C'\fR, |\&\f(CW\*(C`no87\*(C'\fR,
) (rof_escape_sequence|91|as.1|1307|\*(C`no287\*(C'\fR, |\&\f(CW\*(C`no287\*(C'\fR,
) (rof_escape_sequence|91|as.1|1308|\*(C`no387\*(C'\fR, |\&\f(CW\*(C`no387\*(C'\fR,
) (rof_escape_sequence|91|as.1|1309|\*(C`no687\*(C'\fR, |\&\f(CW\*(C`no687\*(C'\fR,
) (rof_escape_sequence|91|as.1|1310|\*(C`cmov\*(C'\fR, |\&\f(CW\*(C`cmov\*(C'\fR,
) (rof_escape_sequence|91|as.1|1311|\*(C`nocmov\*(C'\fR, |\&\f(CW\*(C`nocmov\*(C'\fR,
) (rof_escape_sequence|91|as.1|1312|\*(C`fxsr\*(C'\fR, |\&\f(CW\*(C`fxsr\*(C'\fR,
) (rof_escape_sequence|91|as.1|1313|\*(C`nofxsr\*(C'\fR, |\&\f(CW\*(C`nofxsr\*(C'\fR,
) (rof_escape_sequence|91|as.1|1314|\*(C`mmx\*(C'\fR, |\&\f(CW\*(C`mmx\*(C'\fR,
) (rof_escape_sequence|91|as.1|1315|\*(C`nommx\*(C'\fR, |\&\f(CW\*(C`nommx\*(C'\fR,
) (rof_escape_sequence|91|as.1|1316|\*(C`sse\*(C'\fR, |\&\f(CW\*(C`sse\*(C'\fR,
) (rof_escape_sequence|91|as.1|1317|\*(C`sse2\*(C'\fR, |\&\f(CW\*(C`sse2\*(C'\fR,
) (rof_escape_sequence|91|as.1|1318|\*(C`sse3\*(C'\fR, |\&\f(CW\*(C`sse3\*(C'\fR,
) (rof_escape_sequence|91|as.1|1319|\*(C`sse4a\*(C'\fR, |\&\f(CW\*(C`sse4a\*(C'\fR,
) (rof_escape_sequence|91|as.1|1320|\*(C`ssse3\*(C'\fR, |\&\f(CW\*(C`ssse3\*(C'\fR,
) (rof_escape_sequence|91|as.1|1321|\*(C`sse4.1\*(C'\fR, |\&\f(CW\*(C`sse4.1\*(C'\fR,
) (rof_escape_sequence|91|as.1|1322|\*(C`sse4.2\*(C'\fR, |\&\f(CW\*(C`sse4.2\*(C'\fR,
) (rof_escape_sequence|91|as.1|1323|\*(C`sse4\*(C'\fR, |\&\f(CW\*(C`sse4\*(C'\fR,
) (rof_escape_sequence|91|as.1|1324|\*(C`nosse\*(C'\fR, |\&\f(CW\*(C`nosse\*(C'\fR,
) (rof_escape_sequence|91|as.1|1325|\*(C`nosse2\*(C'\fR, |\&\f(CW\*(C`nosse2\*(C'\fR,
) (rof_escape_sequence|91|as.1|1326|\*(C`nosse3\*(C'\fR, |\&\f(CW\*(C`nosse3\*(C'\fR,
) (rof_escape_sequence|91|as.1|1327|\*(C`nosse4a\*(C'\fR, |\&\f(CW\*(C`nosse4a\*(C'\fR,
) (rof_escape_sequence|91|as.1|1328|\*(C`nossse3\*(C'\fR, |\&\f(CW\*(C`nossse3\*(C'\fR,
) (rof_escape_sequence|91|as.1|1329|\*(C`nosse4.1\*(C'\fR, |\&\f(CW\*(C`nosse4.1\*(C'\fR,
) (rof_escape_sequence|91|as.1|1330|\*(C`nosse4.2\*(C'\fR, |\&\f(CW\*(C`nosse4.2\*(C'\fR,
) (rof_escape_sequence|91|as.1|1331|\*(C`nosse4\*(C'\fR, |\&\f(CW\*(C`nosse4\*(C'\fR,
) (rof_escape_sequence|91|as.1|1332|\*(C`avx\*(C'\fR, |\&\f(CW\*(C`avx\*(C'\fR,
) (rof_escape_sequence|91|as.1|1333|\*(C`avx2\*(C'\fR, |\&\f(CW\*(C`avx2\*(C'\fR,
) (rof_escape_sequence|91|as.1|1334|\*(C`noavx\*(C'\fR, |\&\f(CW\*(C`noavx\*(C'\fR,
) (rof_escape_sequence|91|as.1|1335|\*(C`noavx2\*(C'\fR, |\&\f(CW\*(C`noavx2\*(C'\fR,
) (rof_escape_sequence|91|as.1|1336|\*(C`adx\*(C'\fR, |\&\f(CW\*(C`adx\*(C'\fR,
) (rof_escape_sequence|91|as.1|1337|\*(C`rdseed\*(C'\fR, |\&\f(CW\*(C`rdseed\*(C'\fR,
) (rof_escape_sequence|91|as.1|1338|\*(C`prfchw\*(C'\fR, |\&\f(CW\*(C`prfchw\*(C'\fR,
) (rof_escape_sequence|91|as.1|1339|\*(C`smap\*(C'\fR, |\&\f(CW\*(C`smap\*(C'\fR,
) (rof_escape_sequence|91|as.1|1340|\*(C`mpx\*(C'\fR, |\&\f(CW\*(C`mpx\*(C'\fR,
) (rof_escape_sequence|91|as.1|1341|\*(C`sha\*(C'\fR, |\&\f(CW\*(C`sha\*(C'\fR,
) (rof_escape_sequence|91|as.1|1342|\*(C`rdpid\*(C'\fR, |\&\f(CW\*(C`rdpid\*(C'\fR,
) (rof_escape_sequence|91|as.1|1343|\*(C`ptwrite\*(C'\fR, |\&\f(CW\*(C`ptwrite\*(C'\fR,
) (rof_escape_sequence|91|as.1|1344|\*(C`cet\*(C'\fR, |\&\f(CW\*(C`cet\*(C'\fR,
) (rof_escape_sequence|91|as.1|1345|\*(C`gfni\*(C'\fR, |\&\f(CW\*(C`gfni\*(C'\fR,
) (rof_escape_sequence|91|as.1|1346|\*(C`vaes\*(C'\fR, |\&\f(CW\*(C`vaes\*(C'\fR,
) (rof_escape_sequence|91|as.1|1347|\*(C`vpclmulqdq\*(C'\fR, |\&\f(CW\*(C`vpclmulqdq\*(C'\fR,
) (rof_escape_sequence|91|as.1|1348|\*(C`prefetchwt1\*(C'\fR, |\&\f(CW\*(C`prefetchwt1\*(C'\fR,
) (rof_escape_sequence|91|as.1|1349|\*(C`clflushopt\*(C'\fR, |\&\f(CW\*(C`clflushopt\*(C'\fR,
) (rof_escape_sequence|91|as.1|1350|\*(C`se1\*(C'\fR, |\&\f(CW\*(C`se1\*(C'\fR,
) (rof_escape_sequence|91|as.1|1351|\*(C`clwb\*(C'\fR, |\&\f(CW\*(C`clwb\*(C'\fR,
) (rof_escape_sequence|91|as.1|1352|\*(C`movdiri\*(C'\fR, |\&\f(CW\*(C`movdiri\*(C'\fR,
) (rof_escape_sequence|91|as.1|1353|\*(C`movdir64b\*(C'\fR, |\&\f(CW\*(C`movdir64b\*(C'\fR,
) (rof_escape_sequence|91|as.1|1354|\*(C`enqcmd\*(C'\fR, |\&\f(CW\*(C`enqcmd\*(C'\fR,
) (rof_escape_sequence|91|as.1|1355|\*(C`serialize\*(C'\fR, |\&\f(CW\*(C`serialize\*(C'\fR,
) (rof_escape_sequence|91|as.1|1356|\*(C`tsxldtrk\*(C'\fR, |\&\f(CW\*(C`tsxldtrk\*(C'\fR,
) (rof_escape_sequence|91|as.1|1357|\*(C`kl\*(C'\fR, |\&\f(CW\*(C`kl\*(C'\fR,
) (rof_escape_sequence|91|as.1|1358|\*(C`nokl\*(C'\fR, |\&\f(CW\*(C`nokl\*(C'\fR,
) (rof_escape_sequence|91|as.1|1359|\*(C`widekl\*(C'\fR, |\&\f(CW\*(C`widekl\*(C'\fR,
) (rof_escape_sequence|91|as.1|1360|\*(C`nowidekl\*(C'\fR, |\&\f(CW\*(C`nowidekl\*(C'\fR,
) (rof_escape_sequence|91|as.1|1361|\*(C`hreset\*(C'\fR, |\&\f(CW\*(C`hreset\*(C'\fR,
) (rof_escape_sequence|91|as.1|1362|\*(C`avx512f\*(C'\fR, |\&\f(CW\*(C`avx512f\*(C'\fR,
) (rof_escape_sequence|91|as.1|1363|\*(C`avx512cd\*(C'\fR, |\&\f(CW\*(C`avx512cd\*(C'\fR,
) (rof_escape_sequence|91|as.1|1364|\*(C`avx512er\*(C'\fR, |\&\f(CW\*(C`avx512er\*(C'\fR,
) (rof_escape_sequence|91|as.1|1365|\*(C`avx512pf\*(C'\fR, |\&\f(CW\*(C`avx512pf\*(C'\fR,
) (rof_escape_sequence|91|as.1|1366|\*(C`avx512vl\*(C'\fR, |\&\f(CW\*(C`avx512vl\*(C'\fR,
) (rof_escape_sequence|91|as.1|1367|\*(C`avx512bw\*(C'\fR, |\&\f(CW\*(C`avx512bw\*(C'\fR,
) (rof_escape_sequence|91|as.1|1368|\*(C`avx512dq\*(C'\fR, |\&\f(CW\*(C`avx512dq\*(C'\fR,
) (rof_escape_sequence|91|as.1|1369|\*(C`avx512ifma\*(C'\fR, |\&\f(CW\*(C`avx512ifma\*(C'\fR,
) (rof_escape_sequence|91|as.1|1370|\*(C`avx512vbmi\*(C'\fR, |\&\f(CW\*(C`avx512vbmi\*(C'\fR,
) (rof_escape_sequence|91|as.1|1371|\*(C`avx512_4fmaps\*(C'\fR, |\&\f(CW\*(C`avx512_4fmaps\*(C'\fR,
) (rof_escape_sequence|91|as.1|1372|\*(C`avx512_4vnniw\*(C'\fR, |\&\f(CW\*(C`avx512_4vnniw\*(C'\fR,
) (rof_escape_sequence|91|as.1|1373|\*(C`avx512_vpopcntdq\*(C'\fR, |\&\f(CW\*(C`avx512_vpopcntdq\*(C'\fR,
) (rof_escape_sequence|91|as.1|1374|\*(C`avx512_vbmi2\*(C'\fR, |\&\f(CW\*(C`avx512_vbmi2\*(C'\fR,
) (rof_escape_sequence|91|as.1|1375|\*(C`avx512_vnni\*(C'\fR, |\&\f(CW\*(C`avx512_vnni\*(C'\fR,
) (rof_escape_sequence|91|as.1|1376|\*(C`avx512_bitalg\*(C'\fR, |\&\f(CW\*(C`avx512_bitalg\*(C'\fR,
) (rof_escape_sequence|91|as.1|1377|\*(C`avx512_vp2intersect\*(C'\fR, |\&\f(CW\*(C`avx512_vp2intersect\*(C'\fR,
) (rof_escape_sequence|91|as.1|1378|\*(C`tdx\*(C'\fR, |\&\f(CW\*(C`tdx\*(C'\fR,
) (rof_escape_sequence|91|as.1|1379|\*(C`avx512_bf16\*(C'\fR, |\&\f(CW\*(C`avx512_bf16\*(C'\fR,
) (rof_escape_sequence|91|as.1|1380|\*(C`avx_vnni\*(C'\fR, |\&\f(CW\*(C`avx_vnni\*(C'\fR,
) (rof_escape_sequence|91|as.1|1381|\*(C`avx512_fp16\*(C'\fR, |\&\f(CW\*(C`avx512_fp16\*(C'\fR,
) (rof_escape_sequence|91|as.1|1382|\*(C`noavx512f\*(C'\fR, |\&\f(CW\*(C`noavx512f\*(C'\fR,
) (rof_escape_sequence|91|as.1|1383|\*(C`noavx512cd\*(C'\fR, |\&\f(CW\*(C`noavx512cd\*(C'\fR,
) (rof_escape_sequence|91|as.1|1384|\*(C`noavx512er\*(C'\fR, |\&\f(CW\*(C`noavx512er\*(C'\fR,
) (rof_escape_sequence|91|as.1|1385|\*(C`noavx512pf\*(C'\fR, |\&\f(CW\*(C`noavx512pf\*(C'\fR,
) (rof_escape_sequence|91|as.1|1386|\*(C`noavx512vl\*(C'\fR, |\&\f(CW\*(C`noavx512vl\*(C'\fR,
) (rof_escape_sequence|91|as.1|1387|\*(C`noavx512bw\*(C'\fR, |\&\f(CW\*(C`noavx512bw\*(C'\fR,
) (rof_escape_sequence|91|as.1|1388|\*(C`noavx512dq\*(C'\fR, |\&\f(CW\*(C`noavx512dq\*(C'\fR,
) (rof_escape_sequence|91|as.1|1389|\*(C`noavx512ifma\*(C'\fR, |\&\f(CW\*(C`noavx512ifma\*(C'\fR,
) (rof_escape_sequence|91|as.1|1390|\*(C`noavx512vbmi\*(C'\fR, |\&\f(CW\*(C`noavx512vbmi\*(C'\fR,
) (rof_escape_sequence|91|as.1|1391|\*(C`noavx512_4fmaps\*(C'\fR, |\&\f(CW\*(C`noavx512_4fmaps\*(C'\fR,
) (rof_escape_sequence|91|as.1|1392|\*(C`noavx512_4vnniw\*(C'\fR, |\&\f(CW\*(C`noavx512_4vnniw\*(C'\fR,
) (rof_escape_sequence|91|as.1|1393|\*(C`noavx512_vpopcntdq\*(C'\fR, |\&\f(CW\*(C`noavx512_vpopcntdq\*(C'\fR,
) (rof_escape_sequence|91|as.1|1394|\*(C`noavx512_vbmi2\*(C'\fR, |\&\f(CW\*(C`noavx512_vbmi2\*(C'\fR,
) (rof_escape_sequence|91|as.1|1395|\*(C`noavx512_vnni\*(C'\fR, |\&\f(CW\*(C`noavx512_vnni\*(C'\fR,
) (rof_escape_sequence|91|as.1|1396|\*(C`noavx512_bitalg\*(C'\fR, |\&\f(CW\*(C`noavx512_bitalg\*(C'\fR,
) (rof_escape_sequence|91|as.1|1397|\*(C`noavx512_vp2intersect\*(C'\fR, |\&\f(CW\*(C`noavx512_vp2intersect\*(C'\fR,
) (rof_escape_sequence|91|as.1|1398|\*(C`notdx\*(C'\fR, |\&\f(CW\*(C`notdx\*(C'\fR,
) (rof_escape_sequence|91|as.1|1399|\*(C`noavx512_bf16\*(C'\fR, |\&\f(CW\*(C`noavx512_bf16\*(C'\fR,
) (rof_escape_sequence|91|as.1|1400|\*(C`noavx_vnni\*(C'\fR, |\&\f(CW\*(C`noavx_vnni\*(C'\fR,
) (rof_escape_sequence|91|as.1|1401|\*(C`noavx512_fp16\*(C'\fR, |\&\f(CW\*(C`noavx512_fp16\*(C'\fR,
) (rof_escape_sequence|91|as.1|1402|\*(C`noenqcmd\*(C'\fR, |\&\f(CW\*(C`noenqcmd\*(C'\fR,
) (rof_escape_sequence|91|as.1|1403|\*(C`noserialize\*(C'\fR, |\&\f(CW\*(C`noserialize\*(C'\fR,
) (rof_escape_sequence|91|as.1|1404|\*(C`notsxldtrk\*(C'\fR, |\&\f(CW\*(C`notsxldtrk\*(C'\fR,
) (rof_escape_sequence|91|as.1|1405|\*(C`amx_int8\*(C'\fR, |\&\f(CW\*(C`amx_int8\*(C'\fR,
) (rof_escape_sequence|91|as.1|1406|\*(C`noamx_int8\*(C'\fR, |\&\f(CW\*(C`noamx_int8\*(C'\fR,
) (rof_escape_sequence|91|as.1|1407|\*(C`amx_bf16\*(C'\fR, |\&\f(CW\*(C`amx_bf16\*(C'\fR,
) (rof_escape_sequence|91|as.1|1408|\*(C`noamx_bf16\*(C'\fR, |\&\f(CW\*(C`noamx_bf16\*(C'\fR,
) (rof_escape_sequence|91|as.1|1409|\*(C`amx_tile\*(C'\fR, |\&\f(CW\*(C`amx_tile\*(C'\fR,
) (rof_escape_sequence|91|as.1|1410|\*(C`noamx_tile\*(C'\fR, |\&\f(CW\*(C`noamx_tile\*(C'\fR,
) (rof_escape_sequence|91|as.1|1411|\*(C`nouintr\*(C'\fR, |\&\f(CW\*(C`nouintr\*(C'\fR,
) (rof_escape_sequence|91|as.1|1412|\*(C`nohreset\*(C'\fR, |\&\f(CW\*(C`nohreset\*(C'\fR,
) (rof_escape_sequence|91|as.1|1413|\*(C`vmx\*(C'\fR, |\&\f(CW\*(C`vmx\*(C'\fR,
) (rof_escape_sequence|91|as.1|1414|\*(C`vmfunc\*(C'\fR, |\&\f(CW\*(C`vmfunc\*(C'\fR,
) (rof_escape_sequence|91|as.1|1415|\*(C`smx\*(C'\fR, |\&\f(CW\*(C`smx\*(C'\fR,
) (rof_escape_sequence|91|as.1|1416|\*(C`xsave\*(C'\fR, |\&\f(CW\*(C`xsave\*(C'\fR,
) (rof_escape_sequence|91|as.1|1417|\*(C`xsaveopt\*(C'\fR, |\&\f(CW\*(C`xsaveopt\*(C'\fR,
) (rof_escape_sequence|91|as.1|1418|\*(C`xsavec\*(C'\fR, |\&\f(CW\*(C`xsavec\*(C'\fR,
) (rof_escape_sequence|91|as.1|1419|\*(C`xsaves\*(C'\fR, |\&\f(CW\*(C`xsaves\*(C'\fR,
) (rof_escape_sequence|91|as.1|1420|\*(C`aes\*(C'\fR, |\&\f(CW\*(C`aes\*(C'\fR,
) (rof_escape_sequence|91|as.1|1421|\*(C`pclmul\*(C'\fR, |\&\f(CW\*(C`pclmul\*(C'\fR,
) (rof_escape_sequence|91|as.1|1422|\*(C`fsgsbase\*(C'\fR, |\&\f(CW\*(C`fsgsbase\*(C'\fR,
) (rof_escape_sequence|91|as.1|1423|\*(C`rdrnd\*(C'\fR, |\&\f(CW\*(C`rdrnd\*(C'\fR,
) (rof_escape_sequence|91|as.1|1424|\*(C`f16c\*(C'\fR, |\&\f(CW\*(C`f16c\*(C'\fR,
) (rof_escape_sequence|91|as.1|1425|\*(C`bmi2\*(C'\fR, |\&\f(CW\*(C`bmi2\*(C'\fR,
) (rof_escape_sequence|91|as.1|1426|\*(C`fma\*(C'\fR, |\&\f(CW\*(C`fma\*(C'\fR,
) (rof_escape_sequence|91|as.1|1427|\*(C`movbe\*(C'\fR, |\&\f(CW\*(C`movbe\*(C'\fR,
) (rof_escape_sequence|91|as.1|1428|\*(C`ept\*(C'\fR, |\&\f(CW\*(C`ept\*(C'\fR,
) (rof_escape_sequence|91|as.1|1429|\*(C`lzcnt\*(C'\fR, |\&\f(CW\*(C`lzcnt\*(C'\fR,
) (rof_escape_sequence|91|as.1|1430|\*(C`popcnt\*(C'\fR, |\&\f(CW\*(C`popcnt\*(C'\fR,
) (rof_escape_sequence|91|as.1|1431|\*(C`hle\*(C'\fR, |\&\f(CW\*(C`hle\*(C'\fR,
) (rof_escape_sequence|91|as.1|1432|\*(C`rtm\*(C'\fR, |\&\f(CW\*(C`rtm\*(C'\fR,
) (rof_escape_sequence|91|as.1|1433|\*(C`invpcid\*(C'\fR, |\&\f(CW\*(C`invpcid\*(C'\fR,
) (rof_escape_sequence|91|as.1|1434|\*(C`clflush\*(C'\fR, |\&\f(CW\*(C`clflush\*(C'\fR,
) (rof_escape_sequence|91|as.1|1435|\*(C`mwaitx\*(C'\fR, |\&\f(CW\*(C`mwaitx\*(C'\fR,
) (rof_escape_sequence|91|as.1|1436|\*(C`clzero\*(C'\fR, |\&\f(CW\*(C`clzero\*(C'\fR,
) (rof_escape_sequence|91|as.1|1437|\*(C`wbnoinvd\*(C'\fR, |\&\f(CW\*(C`wbnoinvd\*(C'\fR,
) (rof_escape_sequence|91|as.1|1438|\*(C`pconfig\*(C'\fR, |\&\f(CW\*(C`pconfig\*(C'\fR,
) (rof_escape_sequence|91|as.1|1439|\*(C`waitpkg\*(C'\fR, |\&\f(CW\*(C`waitpkg\*(C'\fR,
) (rof_escape_sequence|91|as.1|1440|\*(C`uintr\*(C'\fR, |\&\f(CW\*(C`uintr\*(C'\fR,
) (rof_escape_sequence|91|as.1|1441|\*(C`cldemote\*(C'\fR, |\&\f(CW\*(C`cldemote\*(C'\fR,
) (rof_escape_sequence|91|as.1|1442|\*(C`rdpru\*(C'\fR, |\&\f(CW\*(C`rdpru\*(C'\fR,
) (rof_escape_sequence|91|as.1|1443|\*(C`mcommit\*(C'\fR, |\&\f(CW\*(C`mcommit\*(C'\fR,
) (rof_escape_sequence|91|as.1|1444|\*(C`sev_es\*(C'\fR, |\&\f(CW\*(C`sev_es\*(C'\fR,
) (rof_escape_sequence|91|as.1|1445|\*(C`lwp\*(C'\fR, |\&\f(CW\*(C`lwp\*(C'\fR,
) (rof_escape_sequence|91|as.1|1446|\*(C`fma4\*(C'\fR, |\&\f(CW\*(C`fma4\*(C'\fR,
) (rof_escape_sequence|91|as.1|1447|\*(C`xop\*(C'\fR, |\&\f(CW\*(C`xop\*(C'\fR,
) (rof_escape_sequence|91|as.1|1448|\*(C`cx16\*(C'\fR, |\&\f(CW\*(C`cx16\*(C'\fR,
) (rof_escape_sequence|91|as.1|1449|\*(C`syscall\*(C'\fR, |\&\f(CW\*(C`syscall\*(C'\fR,
) (rof_escape_sequence|91|as.1|1450|\*(C`rdtscp\*(C'\fR, |\&\f(CW\*(C`rdtscp\*(C'\fR,
) (rof_escape_sequence|91|as.1|1451|\*(C`3dnow\*(C'\fR, |\&\f(CW\*(C`3dnow\*(C'\fR,
) (rof_escape_sequence|91|as.1|1452|\*(C`3dnowa\*(C'\fR, |\&\f(CW\*(C`3dnowa\*(C'\fR,
) (rof_escape_sequence|91|as.1|1453|\*(C`sse4a\*(C'\fR, |\&\f(CW\*(C`sse4a\*(C'\fR,
) (rof_escape_sequence|91|as.1|1454|\*(C`sse5\*(C'\fR, |\&\f(CW\*(C`sse5\*(C'\fR,
) (rof_escape_sequence|91|as.1|1455|\*(C`snp\*(C'\fR, |\&\f(CW\*(C`snp\*(C'\fR,
) (rof_escape_sequence|91|as.1|1456|\*(C`invlpgb\*(C'\fR, |\&\f(CW\*(C`invlpgb\*(C'\fR,
) (rof_escape_sequence|91|as.1|1457|\*(C`tlbsync\*(C'\fR, |\&\f(CW\*(C`tlbsync\*(C'\fR,
) (rof_escape_sequence|91|as.1|1458|\*(C`svme\*(C'\fR and |\&\f(CW\*(C`svme\*(C'\fR and
) (rof_escape_sequence|91|as.1|1459|\*(C`padlock\*(C'\fR. |\&\f(CW\*(C`padlock\*(C'\fR.
) (rof_escape_sequence|91|as.1|1461|\*(C`no\*(C'\fR revoke the respective functionality. |mnemonics starting with \f(CW\*(C`no\*(C'\fR revoke the respective functionality.
) (rof_escape_sequence|91|as.1|1463|\*(C`.arch\*(C'\fR directive is used with \fB\-march\fR, the |When the \f(CW\*(C`.arch\*(C'\fR directive is used with \fB\-march\fR, the
) (rof_escape_sequence|91|as.1|1464|\*(C`.arch\*(C'\fR directive will take precedent. |\&\f(CW\*(C`.arch\*(C'\fR directive will take precedent.
) (rof_escape_sequence|91|as.1|1556|\*(C`.att_mnemonic\*(C'\fR and \f(CW\*(C`.intel_mnemonic\*(C'\fR directives will |The \f(CW\*(C`.att_mnemonic\*(C'\fR and \f(CW\*(C`.intel_mnemonic\*(C'\fR directives will
) (rof_escape_sequence|91|as.1|1565|\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR directives will |The \f(CW\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR directives will
) (rof_escape_sequence|91|as.1|1570|\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR directives will take precedent. |The \f(CW\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR directives will take precedent.
) (rof_escape_sequence|91|as.1|1842|\*(C`jmp\*(C'\fR |Replace identified out-of-range branches with PC-relative \f(CW\*(C`jmp\*(C'\fR
) (rof_escape_sequence|91|as.1|1850|\*(C`jmp\*(C'\fR and \f(CW\*(C`callr\*(C'\fR sequences |and all call instructions with \f(CW\*(C`jmp\*(C'\fR and \f(CW\*(C`callr\*(C'\fR sequences
) (rof_escape_sequence|91|as.1|1868|\*(C`r1\*(C'\fR, |\&\f(CW\*(C`r1\*(C'\fR,
) (rof_escape_sequence|91|as.1|1869|\*(C`r2\*(C'\fR. |\&\f(CW\*(C`r2\*(C'\fR.
) (rof_escape_sequence|91|as.1|1870|\*(C`r1\*(C'\fR. |The default is \f(CW\*(C`r1\*(C'\fR.
) (rof_escape_sequence|91|as.1|1878|\*(C`as\*(C'\fR |shorten the LDI32 instruction to a single LDI. In such case \f(CW\*(C`as\*(C'\fR
) (rof_escape_sequence|91|as.1|1895|\*(C`gp\*(C'\fR register. It is only accepted for targets that |implicitly with the \f(CW\*(C`gp\*(C'\fR register. It is only accepted for targets that
) (rof_escape_sequence|91|as.1|1975|\*(C`nop\*(C'\fR instruction there |instructions or fewer and always schedule a \f(CW\*(C`nop\*(C'\fR instruction there
) (rof_escape_sequence|91|as.1|1992|\*(C`.pdr\*(C'\fR sections. |Control generation of \f(CW\*(C`.pdr\*(C'\fR sections.
) (rof_escape_sequence|91|as.1|2035|\*(C`.module mips16\*(C'\fR at the start of the assembly file. \fB\-no\-mips16\fR |\&\f(CW\*(C`.module mips16\*(C'\fR at the start of the assembly file. \fB\-no\-mips16\fR
) (rof_escape_sequence|91|as.1|2044|\*(C`.module mips16e2\*(C'\fR at the start of the assembly file. |to putting \f(CW\*(C`.module mips16e2\*(C'\fR at the start of the assembly file.
) (rof_escape_sequence|91|as.1|2053|\*(C`.module micromips\*(C'\fR at the start of the assembly file. |\&\f(CW\*(C`.module micromips\*(C'\fR at the start of the assembly file.
) (rof_escape_sequence|91|as.1|2055|\*(C`.module nomicromips\*(C'\fR at the start of the assembly file. |\&\f(CW\*(C`.module nomicromips\*(C'\fR at the start of the assembly file.
) (rof_escape_sequence|91|as.1|2063|\*(C`.module smartmips\*(C'\fR at the start of the assembly |equivalent to putting \f(CW\*(C`.module smartmips\*(C'\fR at the start of the assembly
) (rof_escape_sequence|91|as.1|2212|\*(C`.set insn32\*(C'\fR at |instructions. This is equivalent to putting \f(CW\*(C`.set insn32\*(C'\fR at
) (rof_escape_sequence|91|as.1|2214|\*(C`.set noinsn32\*(C'\fR at the |option. This is equivalent to putting \f(CW\*(C`.set noinsn32\*(C'\fR at the
) (rof_escape_sequence|91|as.1|2724|\*(C`c62x\*(C'\fR, |The following values of \fIarch\fR are accepted: \f(CW\*(C`c62x\*(C'\fR,
) (rof_escape_sequence|91|as.1|2725|\*(C`c64x\*(C'\fR, \f(CW\*(C`c64x+\*(C'\fR, \f(CW\*(C`c67x\*(C'\fR, \f(CW\*(C`c67x+\*(C'\fR, \f(CW\*(C`c674x\*(C'\fR. |\&\f(CW\*(C`c64x\*(C'\fR, \f(CW\*(C`c64x+\*(C'\fR, \f(CW\*(C`c67x\*(C'\fR, \f(CW\*(C`c67x+\*(C'\fR, \f(CW\*(C`c674x\*(C'\fR.
) (rof_escape_sequence|91|as.1|2733|\*(C`Tag_ABI_DSBT\*(C'\fR attribute with a value of 1, indicating that the |\&\f(CW\*(C`Tag_ABI_DSBT\*(C'\fR attribute with a value of 1, indicating that the
) (rof_escape_sequence|91|as.1|2747|\*(C`Tag_ABI_PID\*(C'\fR attribute with a value indicating the form of data |\&\f(CW\*(C`Tag_ABI_PID\*(C'\fR attribute with a value indicating the form of data
) (rof_escape_sequence|91|as.1|2762|\*(C`Tag_ABI_PIC\*(C'\fR attribute with a value of 1, indicating that the |\&\f(CW\*(C`Tag_ABI_PIC\*(C'\fR attribute with a value of 1, indicating that the
) (rof_escape_sequence|91|as.1|2764|\*(C`\-mno\-pic\*(C'\fR option, the default, causes the tag to have a value of |\&\f(CW\*(C`\-mno\-pic\*(C'\fR option, the default, causes the tag to have a value of
) (rof_escape_sequence|91|as.1|2795|\*(C`mcm24\*(C'\fR |\&\f(CW\*(C`mcm24\*(C'\fR
) (rof_escape_sequence|91|as.1|2796|\*(C`mcm\*(C'\fR |\&\f(CW\*(C`mcm\*(C'\fR
) (rof_escape_sequence|91|as.1|2797|\*(C`gr5\*(C'\fR |\&\f(CW\*(C`gr5\*(C'\fR
) (rof_escape_sequence|91|as.1|2798|\*(C`gr6\*(C'\fR |\&\f(CW\*(C`gr6\*(C'\fR
) (rof_escape_sequence|91|as.1|2811|\*(C`L32R\*(C'\fR instructions in the text section. Literals are grouped into |\&\f(CW\*(C`L32R\*(C'\fR instructions in the text section. Literals are grouped into
) (rof_escape_sequence|91|as.1|2812|\*(C`.literal_position\*(C'\fR directives or preceding |pools following \f(CW\*(C`.literal_position\*(C'\fR directives or preceding
) (rof_escape_sequence|91|as.1|2813|\*(C`ENTRY\*(C'\fR instructions. These options only affect literals referenced |\&\f(CW\*(C`ENTRY\*(C'\fR instructions. These options only affect literals referenced
) (rof_escape_sequence|91|as.1|2814|\*(C`L32R\*(C'\fR instructions; literals for absolute mode |via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals for absolute mode
) (rof_escape_sequence|91|as.1|2815|\*(C`L32R\*(C'\fR instructions are handled separately. |\&\f(CW\*(C`L32R\*(C'\fR instructions are handled separately.
) (rof_escape_sequence|91|as.1|2824|\*(C`.literal_position\*(C'\fR directives are not |references, explicit \f(CW\*(C`.literal_position\*(C'\fR directives are not
) (rof_escape_sequence|91|as.1|2827|\*(C`L32R\*(C'\fR instructions at the end. These options only affect |\&\f(CW\*(C`L32R\*(C'\fR instructions at the end. These options only affect
) (rof_escape_sequence|91|as.1|2828|\*(C`L32R\*(C'\fR instructions; literals |literals referenced via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals
) (rof_escape_sequence|91|as.1|2829|\*(C`L32R\*(C'\fR instructions are handled separately. |for absolute mode \f(CW\*(C`L32R\*(C'\fR instructions are handled separately.
) (rof_escape_sequence|91|as.1|2834|\*(C`L32R\*(C'\fR instructions use absolute |Indicate to the assembler whether \f(CW\*(C`L32R\*(C'\fR instructions use absolute
) (rof_escape_sequence|91|as.1|2836|\*(C`L32R\*(C'\fR |addressing option, the default is to use absolute \f(CW\*(C`L32R\*(C'\fR
) (rof_escape_sequence|91|as.1|2837|\*(C`L32R\*(C'\fR relocations |relocations. Otherwise, only the PC-relative \f(CW\*(C`L32R\*(C'\fR relocations
) (rof_escape_sequence|91|as.1|2843|\*(C`LOOP\*(C'\fR that |that the assembler will always align instructions like \f(CW\*(C`LOOP\*(C'\fR that
) (rof_escape_sequence|91|as.1|2874|\*(C`.xtensa.info\*(C'\fR section. ABI tag |Choose ABI tag written to the \f(CW\*(C`.xtensa.info\*(C'\fR section. ABI tag
) (rof_escape_sequence|91|as.1|2891|\*(C`z80\*(C'\fR, |\&\f(CW\*(C`z80\*(C'\fR,
) (rof_escape_sequence|91|as.1|2892|\*(C`z180\*(C'\fR, |\&\f(CW\*(C`z180\*(C'\fR,
) (rof_escape_sequence|91|as.1|2893|\*(C`ez80\*(C'\fR, |\&\f(CW\*(C`ez80\*(C'\fR,
) (rof_escape_sequence|91|as.1|2894|\*(C`gbz80\*(C'\fR, |\&\f(CW\*(C`gbz80\*(C'\fR,
) (rof_escape_sequence|91|as.1|2895|\*(C`z80n\*(C'\fR, |\&\f(CW\*(C`z80n\*(C'\fR,
) (rof_escape_sequence|91|as.1|2896|\*(C`r800\*(C'\fR. |\&\f(CW\*(C`r800\*(C'\fR.
) (rof_escape_sequence|91|as.1|2899|\*(C`\-march=z180+sli+infc\*(C'\fR extends \fIz180\fR with \fISLI\fR instructions and |\&\f(CW\*(C`\-march=z180+sli+infc\*(C'\fR extends \fIz180\fR with \fISLI\fR instructions and
) (rof_escape_sequence|91|as.1|2901|\*(C`full\*(C'\fR (all known instructions), |\&\f(CW\*(C`full\*(C'\fR (all known instructions),
) (rof_escape_sequence|91|as.1|2902|\*(C`adl\*(C'\fR (ADL CPU mode by default, eZ80 only), |\&\f(CW\*(C`adl\*(C'\fR (ADL CPU mode by default, eZ80 only),
) (rof_escape_sequence|91|as.1|2903|\*(C`sli\*(C'\fR (instruction known as \fISLI\fR, \fISLL\fR or \fISL1\fR), |\&\f(CW\*(C`sli\*(C'\fR (instruction known as \fISLI\fR, \fISLL\fR or \fISL1\fR),
) (rof_escape_sequence|91|as.1|2904|\*(C`xyhl\*(C'\fR (instructions with halves of index registers: \fIIXL\fR, \fIIXH\fR, |\&\f(CW\*(C`xyhl\*(C'\fR (instructions with halves of index registers: \fIIXL\fR, \fIIXH\fR,
) (rof_escape_sequence|91|as.1|2906|\*(C`xdcb\*(C'\fR (instructions like \fIRotOp (II+d),R\fR and \fIBitOp n,(II+d),R\fR), |\&\f(CW\*(C`xdcb\*(C'\fR (instructions like \fIRotOp (II+d),R\fR and \fIBitOp n,(II+d),R\fR),
) (rof_escape_sequence|91|as.1|2907|\*(C`infc\*(C'\fR (instruction \fIIN F,(C)\fR or \fIIN (C)\fR), |\&\f(CW\*(C`infc\*(C'\fR (instruction \fIIN F,(C)\fR or \fIIN (C)\fR),
) (rof_escape_sequence|91|as.1|2908|\*(C`outc0\*(C'\fR (instruction \fIOUT (C),0\fR). |\&\f(CW\*(C`outc0\*(C'\fR (instruction \fIOUT (C),0\fR).
) (rof_escape_sequence|91|as.1|2910|\*(C`\-\*(C'\fR revoke the respective functionality: |mnemonics starting with \f(CW\*(C`\-\*(C'\fR revoke the respective functionality:
) (rof_escape_sequence|91|as.1|2911|\*(C`\-march=z80\-full+xyhl\*(C'\fR first removes all default extentions and adds |\&\f(CW\*(C`\-march=z80\-full+xyhl\*(C'\fR first removes all default extentions and adds
) (rof_escape_sequence|91|as.1|2914|\*(C`\-march=z80+xyhl+infc\*(C'\fR is assumed. |If this option is not specified then \f(CW\*(C`\-march=z80+xyhl+infc\*(C'\fR is assumed.
) (rof_escape_sequence|91|as.1|2919|\*(C`.L\*(C'\fR, it is just adds new one. |local label prefix \f(CW\*(C`.L\*(C'\fR, it is just adds new one.
)